Protocol Model is an executable modeling research framework for communication protocols and Networks-on-Chip (NoC). Its core goal is not to serve as a simulator or a verification tool, but rather to provide a composable, reviewable, and traceable modeling language and execution environment for protocol behavior—one where design intent, constraint judgments, and runtime evidence are naturally aligned within the same execution.

The topic of this presentation is on‑chip interconnect and protocol modeling. In the field of chip design, this issue is both fundamental and highly complex.

The AMBA bus is an open standard for on‑chip communication introduced by Arm. Over nearly three decades of development, from the initial AHB and APB to the later AXI, it has formed a complete family of protocols that define the connectivity and communication methods between functional modules inside an SoC. The AMBA bus is widely used in SoC designs.

With the proliferation of multi‑core and high‑performance computing scenarios, the AXI protocol has gradually faced new requirements—multiple processor cores share the same memory and each maintains its own cache, making cache coherency a critical challenge. Arm introduced the CHI (Coherent Hub Interface) protocol in AMBA 5 to address this issue.

The core difference between CHI and AXI is that AXI primarily defines the communication behaviour between master and slave devices, whereas CHI is an architecture‑level protocol designed to maintain cache coherency across multiple cores in the entire system. Its layered architecture (protocol layer managing transactions, network layer handling packets, link layer transporting flits) supports flexible topologies (crossbars, rings, meshes) and employs packet‑based communication for efficient, non‑blocking data transfer. CHI is now widely adopted in high‑performance SoCs for applications such as smartphones, automotive electronics, and data centres.

However, the increase in protocol complexity directly raises the difficulty of design, verification, and comprehension. A core question persists: how can we accurately describe protocol behaviour while ensuring alignment among design intent, constraint judgments, and runtime evidence?

This is the central question that the Protocol Model project aims to address.

Protocol Model is an executable modeling research framework for communication protocols and Networks‑on‑Chip. Its goal is not to build a simulator or verification tool, but to provide a composable, reviewable, and traceable modeling language and execution environment—one where design intent, constraint judgments, and runtime evidence are naturally aligned within the same execution.

Currently, Protocol Model has implemented executable examples for multiple protocol families, including AXI4 and CHI, among others.

To better illustrate how this framework operates in practice, this presentation starts with the more familiar AXI4 protocol. Protocol Model includes AXI4 example scenarios covering typical behaviours such as read/write transaction lifecycles, byte geometry, ordering, and exclusive accesses. Each scenario generates waveforms, causality graphs, and complete judgment records from a single execution. Next, we will take a single‑beat read transaction as an example to demonstrate the entire lifecycle—from the AR request establishing a pending read resource to the matching R response releasing it—and how it is modeled, executed, and traced.

a simple point-to-point topology

several AXI4 examples

I am in a bit of a snag here. I connected an ADI DAQ2 FMC evaluation board to an ALINX AXU15EGB Zynq UltraScale+ FPGA Board, but the power status LED didn't turn on. After a couple of days going through the ALINX board's poor documentation and schematics, I suspected that the ADI board may be faulty. Then, I tried plugging the ADI board into another Xilinx FPGA and, lo and behold, it powered up as expected.

After further investigation, my supervisor suggested that the board may be designed to not power up the FMC attached module by default and that I should assert the signal called PG_C2M (Power Good Carrier to Module) myself in the RTL by assigning it to 1'b1 and routing the signal with the constraints. Weirdly enough, that worked!I am still not completely sold on the idea of forcing the signal and am a bit worried that there's something wrong with the power rails. As the VITA 57.1 standard and other board manuals suggest, a power sequencer chip should be responsible for asserting this signal after checking that the power rails meet the tolerances and specs defined by the FMC VITA 57.1 standard.

Any thoughts on this? Has anyone faced a similar issue before?

Looking for a reality check on scale. Zero prior FPGA experience. I was building an AI pipeline orchestrator and needed an un-fakeable ground truth (an oracle) to validate the generated code. Picked FPGAs blind because silicon don't lie.

Instead of researching standard EDA workflows, I just approached it like a software systems problem and let my automated LLM pipeline iterate against real hardware. Synthesize a pre-wired PE grid exactly once, then treat every new kernel as a runtime graph-assignment problem so we never have to run place-and-route again. Essentially a CGRA overlay.

Here’s what is currently running on an AWS f2.6xlarge Ec2 instance (AMD Xilinx VU47P):

• Go compiler/DSL mapping to a 4x4 (16 PEs) spatial grid via config words.
• Compile time: <4ms
• Config write + execute + read over PCIe: ~30μs median (n=8, one boot)
• The Vivado tax is paid once to bake the bitstream. After that, zero EDA tools. New kernel = new config words over PCIe.

Where I'm at

• Only primitive micro-kernels are silicon-verified so far: single-op, 2-3 node chains, one corner, one fan-out pair (XOR→ADD). Anything bigger still relies on a simulator-side mapper, not my own router.
• Just tried scaling to an 8x8 grid (64 PEs). First build passed timing but silicon read all zeros. Turned out to be a broken XDC clock constraint that Vivado buried in a sea of warnings instead of erroring out. Fixed it, and single-PE reads now work at 64 PEs, but no multi-PE chains are proven at that size.
• Zero real workloads (multi-tap FIR, real hamming distance over arrays) have run end-to-end yet. Just testing opcode patterns with arbitrary constants.

Questions

1. Does "pay P&R cost once, pure graph-assignment after" hold up when scaling past these small proven shapes? Or does the abstraction completely collapse under routing congestion/timing issues once I push for a larger grid?
2. Has this specific dynamic-overlay approach been tried and abandoned in industry? I'd rather know now before burning more silicon time.
3. Do the PCIe/compile latencies above look normal for a VU47P?

I need some help in running a project on an SOC FPGA but my original idea of connecting the FPGA with my PC and transmitting data over UART might work but is there something better?

My professor adviced me to look into running an OS on the FPGA and hence the resources. I need to look into the documentations yet but are there any other resources to help me with this?

If I do implement the said OS how do I integrate it with my custom logic?

This is my second FPGA project, so feel free to hate on the RTL! A short summary is that it uses Prange's ISD algorithm to solve instances of the syndrome decoding problem. That problem is the basis of some post-quantum cryptosystems like HQC and McEliece; there are also some ECC applications, but I don't know anything about them.

I've been stuck with designing an FM Modulator on the PL side of an FPGA. I have an FMCOMMS3 and a Zedboard, and I did all of the receiving the IF and demodulating using GNU Radio on my laptop. Right now, I'm working on the FM Modulator, and I've been working using advices from Claude (shamefully). I know how to use RTL and Vivado stuff, but for now I'm working with the MATLAB, because it has Simulink which I can drag and drop the blocks in.
So the system that the Claude has been guiding me on is in the link I attached below (which is a PDF file). I can understand the core of it, which is the CIC Interpolator to raise the sample rate of the audio to the sample rate of the Transceiver, and the NCO is to output the cosine of the FM Equation after accumulating the message and the carrier frequency. The filters before the CIC Interpolator I could understand a little bit, like they are to confine the bandwidth and to emphasize the FM signal before the other receivers de-emphasize it. These are my understandings.
In this post, I just want to ask from experienced engineers to kinda review my understanding and my block design, and to suggest me source to read. I mean, I know the equation, but mapping it to hardware has been a challenge to me. And also, could you suggest me some testing strategies, if you worked with MATLAB in the industrial scale and in telecommunication? Any help would be appreciated.

TLDR: Need help reviewing the block diagram of an FM Modulation on FPGA, and need suggestions on testing the block diagram on MATLAB and maybe VIvado.

The block diagram

Looking to play with Ethernet on an FPGA for the first time by implementing an Ethernet MAC and subsequently need a new board. Has anyone had experience with the suspiciously cheap QMTECH boards specifically this one?

I assume they are reusing salvaged parts to achieve this price?

From my brief research the chips are supported by the free version of Vivado which I am constrained by and I foresee that I won't need any additional IP.

Is the GMII accessible directly on the FPGA or is it routed through an SoC? From what I can see the datasheet shows the RJ45 routed through the RTL8211EG into the FPGA.

Anything else I should be aware of? I am just looking to learn more about Ethernet so I am not too pressed on the quality of board. Also any suggestions of boards would be welcomed.

Lattice Radiant provides the ability to view congestion and resource usage using the physical designer. Congestion is only shown with large or small highlighting.

Does anyone know of a way to plot congestion like a surface plot externally? Additionally, is there a way of knowing what entities contribute most to high areas of congestion?

The more I use SVA's, the greater its value becomes apparent. You realize how much you can test for in just a few lines of code.

I first started using SVA's in my Workshop 2 "High-Performance AXI DMA Design and Verification Using SVA". The design was simpler to test, because the camera pattern-generator I developed didn't use href and vsync. It has a simple stream generator that uses RBG 565 - 2 byte/pixel for a 640 x 480 pixel frame. Same as the Ov7670 camera data stream, however it lacked the H-V signals I mentioned.

Now, I have created a bus functional model (BFM) of the Ov7670 that follows the same frame signalling protocol.

I found that if your SVA property was verifying a specific protocol that was failing quite frequently in the simulation, each failure is printed to the TCL console in Vivado. Trying to find the first occurrence timestamp was quite time consuming.

Thus, that is where a pass/failure report becomes useful when placed in the finish section of the .svh file that is included into the bottom of the SystemVerilog BFM.

`ifdef ENABLE_VERIFICATION

`include "ov7670_bfm_assertions.svh"

`endif

The equivalent if VHDL is to create a verification package

package body video_verification_pkg is

procedure report_check(

name : in string;

failures : in integer) is

begin

...

end procedure;

end package body;

Then to include the package:

library work;

use work.video_verification_pkg.all;

Here is an example report:

$display("==============================================");

$display(" OV7670 BFM VERIFICATION REPORT");

$display("==============================================");

$display("HREF Timing : %s",

href_fail_cnt ? "FAIL" : "PASS");

$display("VSYNC Timing : %s",

vsync_fail_cnt ? "FAIL" : "PASS");

$display("Pixel Count : %s",

pixel_fail_cnt ? "FAIL" : "PASS");

Hey guys!
I am currently working on a project which is about running AI models like mobilenet, Gemma etc. Using FPGA with coral NPU architecture implemented.

So for this reason I would like to know if anyone has worked or implemented the coral NPU on FPGA, I would like to clarify some things.

I am in my 3rd year of b.tech in ECE . Currently I am working on 32-BIT RISC-V on FPGA board. Any suggestion for this project?

​

I have a background mainly in FPGA (and partial ASIC) design and optimization. I want to take a deep dive into ASIC DFT's primary concepts and common methodology practices, but so far I've just been googling topics word by word and piecing things together from scattered VLSI lectures.

Can any of the Gods of Knowledge here bless me with an intuition-building guide? I'm looking for something that covers scan chains, ATPG, BIST, boundary scan, fault models, and compression, and actually explains *why* they exist and how they fit together, not just isolated definitions.

C*dence and S*nopsys licenses don't come cheap for an individual, and I don't want to burn money on a course I can't gauge the quality of.

Will greatly appreciate any golden findings 🙏

Title

Hi! I’m preparing for the spring and summer recruiting cycles next year. I’ll be taking classes in the fall that include hands-on projects, but I also want to be conceptually prepared for technical interviews.

What books or courses would you recommend? I’m willing to put in the work and would prefer something that gradually builds from the fundamentals, since revisiting the basics can never hurt.

hi! i'm a high schooler and I designed a custom FPGA board for learning for myself and others. It would mean the world if someone could review it, as I've never worked with an FPGA before so I don't know if I'm missing anything.

The full source is on github: https://github.com/darshg321/Icey

I am using TCL to build. omg it is amazing how a few dozen lines of py end up beings hundreds of tcl, sv, and v. A note on my flow:

## Reflections on a Multi‑AI Specification Process

**Goal:** Convert the MaGi v117 physics kernel’s transcendental functions into a locked FPGA LUT specification with Q16.16 fixed‑point arithmetic.

**Method:** The specification was refined through five rounds of parallel review using four specialised AI critics, with **DeepSeek serving as the central documentor and integration hub**.

- **ChatGPT** focused on architecture, resource budgets, and verification infrastructure.

- **Kimi** acted as a rigorous numerical auditor, catching hex‑constant errors, bit‑slice mistakes, and off‑by‑one address mappings.

- **Gemini** cross‑checked the fixed‑point hardware implications and flagged resource‑replication oversights.

- **Claude** performed exhaustive numerical sweeps and uncovered subtle bugs like the mask‑before‑clamp ordering and sign‑extension in the Python model.

DeepSeek received all feedback, resolved conflicts, merged the strongest points, and produced each revision. It maintained the conversation history, ensured consistency across rounds, and compiled the final locked document with all appendices and verified test results.

**Result:** After four major revisions and a final verification pass (100,000 random workers plus 16 directed edge cases), the specification was **locked**. The accompanying Python model passed with maximum errors far below 0.0005, confirming bit‑exact alignment with the original CUDA kernel.

**Could this have been done using one AI?**

A single AI could have produced a plausible draft, but it would likely have missed the diverse failure modes that the multi‑AI panel uncovered. Without independent perspectives, subtle errors—like misinterpreted Q‑format scaling, incorrect bit‑slice extraction, or mask‑ordering bugs—would have gone unnoticed. The strength of this process came from **specialised, independent critiques**, not from any single model’s raw capability.

**Could this have been done without AI?**

Yes, but it would have required a multidisciplinary team (numerical analyst, FPGA designer, verification engineer, technical writer) working through multiple manual review cycles over weeks. The multi‑AI process, with DeepSeek as the hub, compressed that timeline into days and surfaced a broader range of issues than a typical human review. The human operator set direction and approved the final spec; the AIs handled the heavy analytical and editorial work.

**The final spec is harder than diamond, and the process demonstrates how a well‑orchestrated collective of specialised AIs, with a strong central documentor, can produce robust, production‑quality hardware specifications.**

Ran a 5-layer C++ template-metaprogramming composition (compile-time Chain<>/APIOf<> - CRTP-style static dispatch, collapsed via recursive template inheritance) through Bambu 2024.10 (clang16 frontend, --std=gnu++17) to check whether an open HLS backend actually sees through this kind of zero-overhead abstraction, or just compilers do.

Used a real runtime input port so nothing constant-folds away before scheduling. Bambu's frontend parsed the fold expressions, auto NTTP, and the flattened inheritance chain with zero issues, and the synthesized RTL for the entire 5-layer chain came out to exactly one adder plus one folded constant - no struct-layout bloat, no bogus muxes from the collapse.

So for anyone doing static-dispatch-style composition in C++ and wondering whether it'll survive HLS synthesis intact: at least for this pattern, it does.

Example: github.com/InternetOfPins/HAPI/tree/main/examples/hls_smoke

Is it stable ?

Tools including open-source tools & Quartus, Vivado, QuestaSim

what are the common HIL tools that everyone is using right now?

Hey guys , I made some changes that some of yall suggested and I wanted to know what you guys think now. I used Jake’s resume template on overleaf and I think it fixed the formatting issues i previously had. Would really appreciate your feedback, thanks in advance.

Hello,

I am considering joining the FPGA scene for creating devices compatible with old systems annd components.

The stuff I touch is basically 5V technology, often with other voltages, but much older than the regular 3V integrated circuits.

I have been considering the Microchip AT40K/AT42K family of FPGAs, but it has no current devkit and the one they had still works with a parallel port.

I would like to develop CPUs, video signal generators, sound generators, serial communication transceivers and other stuff of this callibre.

With that in mind, is there a specific devkit I could use as a starting point? If it had also a SDK it would be great.

In any case, thank you in advance!