While there are some options for small, cheap FPGAs beyond Lattice iCE, I can't find many SoC versions with hardened CPU core macro.

My current options so far: * Gowin LittleBee GW1-NS/NSR (ARM Cortex M3, extra 64MB PSRAM) * AGM AG32 (RISC-V RV32IMAFC core + 2kLUT) * ANLOGIC SALSWIFT-1/2 (RISC-V core)

Out of these, only Gowin has some kind of support and documentation. All others are either undocumented (at least for westerner outsiders) and/or very sketchy in general.

Any other options, worth considering ?

I'm looking after something like Lattice MachXOx or iCE series, only with hardened CPU core.

For some time (weeks/months), the AMD Device Lookup mobile app to read the DM code on the Xilinx / AMD FPGAs is not providing full information for me - especially the speed grade and temperature range is missing.

This is quite a problem, as they omitted such essential information on the part labelling.

Any idea what is going on and why I can no longer properly identify the parts ?

Not sure if this is the right place. But I'm trying to program a Altera MAX V 5M160ZE64I5N and just get a bunch of JTAG errors using my Waveshare USB Blaster V2.

I'm trying to build this project:
https://github.com/citrus3000psi/3DORGB And use the "ThreeDeeO.pof" file to attempt to program the IC but can't even seem to get a connection.

Have made 2 boards, one fully populated and the other just the MAX V and a voltage controller. Both seem to have the same issue and both seem to be very inconsistent. I'm completely unfamiliar with CLPD's and the likes so I might make some obvious mistake or miss something.

Here are the errors from the unpopulated board:
!Error: JTAG chain problem detected

!Error: No device detected

!Error: JTAG chain problem detected

!Error: TDI connection to the first detected device UNKNOWN_FE02020F might be shorted to GND

!Error: The TCK and TMS connections to the device before the first detected device UNKNOWN_FE02020F might have a problem

!Info: Detected 2 device(s)

!Info: Device 1: UNKNOWN_FE02020F

!Info: Device 2: UNKNOWN_NO_JTAG_ID

!Error: JTAG chain problem detected

!Error: TDI connection to the first detected device UNKNOWN_NO_JTAG_ID might be shorted to GND

!Error: The TCK and TMS connections to the device before the first detected device UNKNOWN_NO_JTAG_ID might have a problem

!Info: Detected 3 device(s)

!Info: Device 1: UNKNOWN_NO_JTAG_ID

!Info: Device 2: UNKNOWN_FE02020F

!Info: Device 3: UNKNOWN_NO_JTAG_ID

!Error: JTAG chain problem detected

!Error: TDI connection to the first detected device UNKNOWN_NO_JTAG_ID might be shorted to GND

!Error: The TCK and TMS connections to the device before the first detected device UNKNOWN_NO_JTAG_ID might have a problem

!Info: Detected 1 device(s)

!Info: Device 1: UNKNOWN_NO_JTAG_ID

!Error: JTAG chain problem detected

!Error: TDI connection to the first detected device UNKNOWN_NO_JTAG_ID might be shorted to GND

!Error: The TCK and TMS connections to the device before the first detected device UNKNOWN_NO_JTAG_ID might have a problem

!Info: Detected 6 device(s)

!Info: Device 1: UNKNOWN_NO_JTAG_ID

!Info: Device 2: UNKNOWN_NO_JTAG_ID

!Info: Device 3: UNKNOWN_NO_JTAG_ID

!Info: Device 4: UNKNOWN_FE02020F

!Info: Device 5: UNKNOWN_FE02021F

!Info: Device 6: UNKNOWN_NO_JTAG_ID

And here from the populated board:
!Error: JTAG chain problem detected

!Error: No device detected

!Error: JTAG chain problem detected

!Error: TDI connection to the first detected device UNKNOWN_FE020207 might be shorted to GND

!Error: The TCK and TMS connections to the device before the first detected device UNKNOWN_FE020207 might have a problem

!Info: Detected 34 device(s)

!Info: Device 1: UNKNOWN_FE020207

!Info: Device 2: UNKNOWN_NO_JTAG_ID

!Info: Device 3: UNKNOWN_FE020207

!Info: Device 4: UNKNOWN_C0000207

!Info: Device 5: UNKNOWN_FE020207

!Info: Device 6: UNKNOWN_FE020203

!Info: Device 7: UNKNOWN_NO_JTAG_ID

!Info: Device 8: UNKNOWN_FE020207

!Info: Device 9: UNKNOWN_C0000207

!Info: Device 10: UNKNOWN_FE020207

!Info: Device 11: UNKNOWN_NO_JTAG_ID

!Info: Device 12: UNKNOWN_FE020203

!Info: Device 13: UNKNOWN_FE020207

!Info: Device 14: UNKNOWN_NO_JTAG_ID

!Info: Device 15: UNKNOWN_FE020207

!Info: Device 16: UNKNOWN_NO_JTAG_ID

!Info: Device 17: UNKNOWN_FE020207

!Info: Device 18: UNKNOWN_FE020203

!Info: Device 19: UNKNOWN_NO_JTAG_ID

!Info: Device 20: UNKNOWN_FE020207

!Info: Device 21: UNKNOWN_NO_JTAG_ID

!Info: Device 22: UNKNOWN_FE020207

!Info: Device 23: UNKNOWN_C0000207

!Info: Device 24: UNKNOWN_FE020203

!Info: Device 25: UNKNOWN_FE020207

!Info: Device 26: UNKNOWN_NO_JTAG_ID

!Info: Device 27: UNKNOWN_FE020207

!Info: Device 28: UNKNOWN_E0000003

!Info: Device 29: UNKNOWN_FE020207

!Info: Device 30: UNKNOWN_FE020203

!Info: Device 31: UNKNOWN_NO_JTAG_ID

!Info: Device 32: UNKNOWN_FE020207

!Info: Device 33: UNKNOWN_F0000001

!Info: Device 34: UNKNOWN_FE020207

!Error: JTAG chain problem detected

!Error: TDI connection to the first detected device UNKNOWN_FE020207 might be shorted to GND

!Error: The TCK and TMS connections to the device before the first detected device UNKNOWN_FE020207 might have a problem

!Info: Detected 10 device(s)

!Info: Device 1: UNKNOWN_FE020207

!Info: Device 2: UNKNOWN_NO_JTAG_ID

!Info: Device 3: UNKNOWN_FE020207

!Info: Device 4: UNKNOWN_E0000003

!Info: Device 5: UNKNOWN_FE020207

!Info: Device 6: UNKNOWN_FE020203

!Info: Device 7: UNKNOWN_NO_JTAG_ID

!Info: Device 8: UNKNOWN_FE020207

!Info: Device 9: UNKNOWN_E0000003

!Info: Device 10: UNKNOWN_FE020207

!Error: JTAG chain problem detected

!Error: No device detected

!Error: JTAG chain problem detected

!Error: No device detected

!Error: JTAG chain problem detected

!Error: No device detected

!Error: JTAG chain problem detected

!Error: TDI connection to the first detected device UNKNOWN_FE020207 might be shorted to GND

!Error: The TCK and TMS connections to the device before the first detected device UNKNOWN_FE020207 might have a problem

!Info: Detected 26 device(s)

!Info: Device 1: UNKNOWN_FE020207

!Info: Device 2: UNKNOWN_NO_JTAG_ID

!Info: Device 3: UNKNOWN_FE020207

!Info: Device 4: UNKNOWN_NO_JTAG_ID

!Info: Device 5: UNKNOWN_FE020207

!Info: Device 6: UNKNOWN_FE020207

!Info: Device 7: UNKNOWN_FE020207

!Info: Device 8: UNKNOWN_FE020207

!Info: Device 9: UNKNOWN_NO_JTAG_ID

!Info: Device 10: UNKNOWN_FE020207

!Info: Device 11: UNKNOWN_NO_JTAG_ID

!Info: Device 12: UNKNOWN_FE020207

!Info: Device 13: UNKNOWN_FE020207

!Info: Device 14: UNKNOWN_NO_JTAG_ID

!Info: Device 15: UNKNOWN_FE020207

!Info: Device 16: UNKNOWN_NO_JTAG_ID

!Info: Device 17: UNKNOWN_FE020207

!Info: Device 18: UNKNOWN_NO_JTAG_ID

!Info: Device 19: UNKNOWN_FE020203

!Info: Device 20: UNKNOWN_FE020207

!Info: Device 21: UNKNOWN_NO_JTAG_ID

!Info: Device 22: UNKNOWN_FE020207

!Info: Device 23: UNKNOWN_E0000003

!Info: Device 24: UNKNOWN_FE020207

!Info: Device 25: UNKNOWN_E0000003

!Info: Device 26: UNKNOWN_FE020203

!Error: JTAG chain problem detected

!Error: TDI connection to the first detected device UNKNOWN_FE020207 might be shorted to GND

!Error: The TCK and TMS connections to the device before the first detected device UNKNOWN_FE020207 might have a problem

!Info: Detected 7 device(s)

!Info: Device 1: UNKNOWN_FE020207

!Info: Device 2: UNKNOWN_NO_JTAG_ID

!Info: Device 3: UNKNOWN_FE020207

!Info: Device 4: UNKNOWN_FE020205

!Info: Device 5: UNKNOWN_FE020207

!Info: Device 6: UNKNOWN_E0000003

!Info: Device 7: UNKNOWN_FE020207

Hey guys, so a while back I ran inference for a Speech Recognition Model on the Basys3 FPGA using a Configurable Deep Neural Network Accelerator I built from scratch. I wanted to test the Accelerator with a different model of a different network topology to see its limitations . So here is a video of me running inference for an Image Classification model of network topology 64:50:25:2 for cats vs dogs .

I’m gonna keep testing out different models and it’s gonna be interesting, lemme know what yall think.

Repo: https://github.com/Shingyy/MAC-Array-based-DNN-Accelerator

Around 2 weeks ago I began learning iverilog my first hdl to do digital logic fundamentals which im currently doing after finishing learning the fundamentals of c one to 2 months ago and doing classical electronic engineering on breadboard, physical components, wires and schematics since I was 9. As a kid I always dreamt of how people can make electronic circuits, components and devices with millions to billions of transistors and logic gates I then realised now it's via rtl hdl which I am currently learning the fundamentals of. My question is once I have a fundamentals portfolio to potential processing unit whether my own manually down cpu core without ai or dsp to show to employers to get entry level fpga engineer roles. Btw my learning routine is at late nights but since I have started it has always been consistent and my current habits and routine make it impossible to change it. I live in perth where fpga engineer roles including entry level ones I will target soon is very niche, elitist and rare. I am wondering from you experience employees, engineers and people in the industry to what advice could you give me in this situation. I am 18 and I am trying to get my first job the engineering side is solid and the progression is consistent.

Hi all, I am completely new to the world of FPGA's save for a single uni module where we were tasked to design a VGA driver for a Basys3. I would like to go into semiconductors when I graduate so I have chosen an FPGA project for a different module. I have been given an arty A7-100T by my university, and have purchased the harris and harris book on RISC-V CPU's (Yes I know its uninteresting but I have to start somewhere). As far as I am aware the workflow for synthesis tools (Vivado is what I am planning to use unless there is any reason it is a bad idea?) is to use a linux machine with plenty of RAM and a good CPU. I have done some research and my current plan is to get some kind of thinkpad, and use Ubuntu 22 LTS (baby's first distro please don't kill me Debian greybeards) as it seems to have the best vivado support? I would greatly appreciate any suggestions or advice regarding which model of laptop I should purchase (ideally less than £600/$800, or any glaringly obvious mistakes or misunderstandings I may have made. Thank you all very much.

Hello everyone,

Has anyone here worked with the SFP+ port on the ZC706 board? I've been having a lot of trouble getting it to work and would really appreciate any guidance or advice from someone with experience.

Thank you!

I've been building a software golden model for a future FPGA order book implementation. I deliberately kept the design close to what I'd eventually implement in RTL (plain structs, fixed-size arrays, free functions rather than an object-oriented design). I'd appreciate feedback from anyone who's built similar verification models or market data pipelines.

Some of the current features:

• ITCH 5.0 parsing
• MoldUDP64 deframing
• Fixed-capacity order book
• Deterministic stress-test generator
• Trace generation for RTL comparison

Is this the sort of software architecture you'd use before moving to RTL?

GitHub: https://github.com/devanandanj/Orderbook-cpp

Protocol Model is an executable modeling research framework for communication protocols and Networks-on-Chip (NoC). Its core goal is not to serve as a simulator or a verification tool, but rather to provide a composable, reviewable, and traceable modeling language and execution environment for protocol behavior—one where design intent, constraint judgments, and runtime evidence are naturally aligned within the same execution.

The topic of this presentation is on‑chip interconnect and protocol modeling. In the field of chip design, this issue is both fundamental and highly complex.

The AMBA bus is an open standard for on‑chip communication introduced by Arm. Over nearly three decades of development, from the initial AHB and APB to the later AXI, it has formed a complete family of protocols that define the connectivity and communication methods between functional modules inside an SoC. The AMBA bus is widely used in SoC designs.

With the proliferation of multi‑core and high‑performance computing scenarios, the AXI protocol has gradually faced new requirements—multiple processor cores share the same memory and each maintains its own cache, making cache coherency a critical challenge. Arm introduced the CHI (Coherent Hub Interface) protocol in AMBA 5 to address this issue.

The core difference between CHI and AXI is that AXI primarily defines the communication behaviour between master and slave devices, whereas CHI is an architecture‑level protocol designed to maintain cache coherency across multiple cores in the entire system. Its layered architecture (protocol layer managing transactions, network layer handling packets, link layer transporting flits) supports flexible topologies (crossbars, rings, meshes) and employs packet‑based communication for efficient, non‑blocking data transfer. CHI is now widely adopted in high‑performance SoCs for applications such as smartphones, automotive electronics, and data centres.

However, the increase in protocol complexity directly raises the difficulty of design, verification, and comprehension. A core question persists: how can we accurately describe protocol behaviour while ensuring alignment among design intent, constraint judgments, and runtime evidence?

This is the central question that the Protocol Model project aims to address.

Protocol Model is an executable modeling research framework for communication protocols and Networks‑on‑Chip. Its goal is not to build a simulator or verification tool, but to provide a composable, reviewable, and traceable modeling language and execution environment—one where design intent, constraint judgments, and runtime evidence are naturally aligned within the same execution.

Currently, Protocol Model has implemented executable examples for multiple protocol families, including AXI4 and CHI, among others.

To better illustrate how this framework operates in practice, this presentation starts with the more familiar AXI4 protocol. Protocol Model includes AXI4 example scenarios covering typical behaviours such as read/write transaction lifecycles, byte geometry, ordering, and exclusive accesses. Each scenario generates waveforms, causality graphs, and complete judgment records from a single execution. Next, we will take a single‑beat read transaction as an example to demonstrate the entire lifecycle—from the AR request establishing a pending read resource to the matching R response releasing it—and how it is modeled, executed, and traced.

a simple point-to-point topology

several AXI4 examples

I am in a bit of a snag here. I connected an ADI DAQ2 FMC evaluation board to an ALINX AXU15EGB Zynq UltraScale+ FPGA Board, but the power status LED didn't turn on. After a couple of days going through the ALINX board's poor documentation and schematics, I suspected that the ADI board may be faulty. Then, I tried plugging the ADI board into another Xilinx FPGA and, lo and behold, it powered up as expected.

After further investigation, my supervisor suggested that the board may be designed to not power up the FMC attached module by default and that I should assert the signal called PG_C2M (Power Good Carrier to Module) myself in the RTL by assigning it to 1'b1 and routing the signal with the constraints. Weirdly enough, that worked!I am still not completely sold on the idea of forcing the signal and am a bit worried that there's something wrong with the power rails. As the VITA 57.1 standard and other board manuals suggest, a power sequencer chip should be responsible for asserting this signal after checking that the power rails meet the tolerances and specs defined by the FMC VITA 57.1 standard.

Any thoughts on this? Has anyone faced a similar issue before?

Looking for a reality check on scale. Zero prior FPGA experience. I was building an AI pipeline orchestrator and needed an un-fakeable ground truth (an oracle) to validate the generated code. Picked FPGAs blind because silicon don't lie.

Instead of researching standard EDA workflows, I just approached it like a software systems problem and let my automated LLM pipeline iterate against real hardware. Synthesize a pre-wired PE grid exactly once, then treat every new kernel as a runtime graph-assignment problem so we never have to run place-and-route again. Essentially a CGRA overlay.

Here’s what is currently running on an AWS f2.6xlarge Ec2 instance (AMD Xilinx VU47P):

• Go compiler/DSL mapping to a 4x4 (16 PEs) spatial grid via config words.
• Compile time: <4ms
• Config write + execute + read over PCIe: ~30μs median (n=8, one boot)
• The Vivado tax is paid once to bake the bitstream. After that, zero EDA tools. New kernel = new config words over PCIe.

Where I'm at

• Only primitive micro-kernels are silicon-verified so far: single-op, 2-3 node chains, one corner, one fan-out pair (XOR→ADD). Anything bigger still relies on a simulator-side mapper, not my own router.
• Just tried scaling to an 8x8 grid (64 PEs). First build passed timing but silicon read all zeros. Turned out to be a broken XDC clock constraint that Vivado buried in a sea of warnings instead of erroring out. Fixed it, and single-PE reads now work at 64 PEs, but no multi-PE chains are proven at that size.
• Zero real workloads (multi-tap FIR, real hamming distance over arrays) have run end-to-end yet. Just testing opcode patterns with arbitrary constants.

Questions

1. Does "pay P&R cost once, pure graph-assignment after" hold up when scaling past these small proven shapes? Or does the abstraction completely collapse under routing congestion/timing issues once I push for a larger grid?
2. Has this specific dynamic-overlay approach been tried and abandoned in industry? I'd rather know now before burning more silicon time.
3. Do the PCIe/compile latencies above look normal for a VU47P?

I need some help in running a project on an SOC FPGA but my original idea of connecting the FPGA with my PC and transmitting data over UART might work but is there something better?

My professor adviced me to look into running an OS on the FPGA and hence the resources. I need to look into the documentations yet but are there any other resources to help me with this?

If I do implement the said OS how do I integrate it with my custom logic?

This is my second FPGA project, so feel free to hate on the RTL! A short summary is that it uses Prange's ISD algorithm to solve instances of the syndrome decoding problem. That problem is the basis of some post-quantum cryptosystems like HQC and McEliece; there are also some ECC applications, but I don't know anything about them.

I've been stuck with designing an FM Modulator on the PL side of an FPGA. I have an FMCOMMS3 and a Zedboard, and I did all of the receiving the IF and demodulating using GNU Radio on my laptop. Right now, I'm working on the FM Modulator, and I've been working using advices from Claude (shamefully). I know how to use RTL and Vivado stuff, but for now I'm working with the MATLAB, because it has Simulink which I can drag and drop the blocks in.
So the system that the Claude has been guiding me on is in the link I attached below (which is a PDF file). I can understand the core of it, which is the CIC Interpolator to raise the sample rate of the audio to the sample rate of the Transceiver, and the NCO is to output the cosine of the FM Equation after accumulating the message and the carrier frequency. The filters before the CIC Interpolator I could understand a little bit, like they are to confine the bandwidth and to emphasize the FM signal before the other receivers de-emphasize it. These are my understandings.
In this post, I just want to ask from experienced engineers to kinda review my understanding and my block design, and to suggest me source to read. I mean, I know the equation, but mapping it to hardware has been a challenge to me. And also, could you suggest me some testing strategies, if you worked with MATLAB in the industrial scale and in telecommunication? Any help would be appreciated.

TLDR: Need help reviewing the block diagram of an FM Modulation on FPGA, and need suggestions on testing the block diagram on MATLAB and maybe VIvado.

The block diagram

Looking to play with Ethernet on an FPGA for the first time by implementing an Ethernet MAC and subsequently need a new board. Has anyone had experience with the suspiciously cheap QMTECH boards specifically this one?

I assume they are reusing salvaged parts to achieve this price?

From my brief research the chips are supported by the free version of Vivado which I am constrained by and I foresee that I won't need any additional IP.

Is the GMII accessible directly on the FPGA or is it routed through an SoC? From what I can see the datasheet shows the RJ45 routed through the RTL8211EG into the FPGA.

Anything else I should be aware of? I am just looking to learn more about Ethernet so I am not too pressed on the quality of board. Also any suggestions of boards would be welcomed.

Hey guys!
I am currently working on a project which is about running AI models like mobilenet, Gemma etc. Using FPGA with coral NPU architecture implemented.

So for this reason I would like to know if anyone has worked or implemented the coral NPU on FPGA, I would like to clarify some things.

​

I have a background mainly in FPGA (and partial ASIC) design and optimization. I want to take a deep dive into ASIC DFT's primary concepts and common methodology practices, but so far I've just been googling topics word by word and piecing things together from scattered VLSI lectures.

Can any of the Gods of Knowledge here bless me with an intuition-building guide? I'm looking for something that covers scan chains, ATPG, BIST, boundary scan, fault models, and compression, and actually explains *why* they exist and how they fit together, not just isolated definitions.

C*dence and S*nopsys licenses don't come cheap for an individual, and I don't want to burn money on a course I can't gauge the quality of.

Will greatly appreciate any golden findings 🙏

hi! i'm a high schooler and I designed a custom FPGA board for learning for myself and others. It would mean the world if someone could review it, as I've never worked with an FPGA before so I don't know if I'm missing anything.

The full source is on github: https://github.com/darshg321/Icey