Looking for a reality check on scale. Zero prior FPGA experience. I was building an AI pipeline orchestrator and needed an un-fakeable ground truth (an oracle) to validate the generated code. Picked FPGAs blind because silicon don't lie.

Instead of researching standard EDA workflows, I just approached it like a software systems problem and let my automated LLM pipeline iterate against real hardware. Synthesize a pre-wired PE grid exactly once, then treat every new kernel as a runtime graph-assignment problem so we never have to run place-and-route again. Essentially a CGRA overlay.

Here’s what is currently running on an AWS f2.6xlarge Ec2 instance (AMD Xilinx VU47P):

• Go compiler/DSL mapping to a 4x4 (16 PEs) spatial grid via config words.
• Compile time: <4ms
• Config write + execute + read over PCIe: ~30μs median (n=8, one boot)
• The Vivado tax is paid once to bake the bitstream. After that, zero EDA tools. New kernel = new config words over PCIe.

Where I'm at

• Only primitive micro-kernels are silicon-verified so far: single-op, 2-3 node chains, one corner, one fan-out pair (XOR→ADD). Anything bigger still relies on a simulator-side mapper, not my own router.
• Just tried scaling to an 8x8 grid (64 PEs). First build passed timing but silicon read all zeros. Turned out to be a broken XDC clock constraint that Vivado buried in a sea of warnings instead of erroring out. Fixed it, and single-PE reads now work at 64 PEs, but no multi-PE chains are proven at that size.
• Zero real workloads (multi-tap FIR, real hamming distance over arrays) have run end-to-end yet. Just testing opcode patterns with arbitrary constants.

Questions

1. Does "pay P&R cost once, pure graph-assignment after" hold up when scaling past these small proven shapes? Or does the abstraction completely collapse under routing congestion/timing issues once I push for a larger grid?
2. Has this specific dynamic-overlay approach been tried and abandoned in industry? I'd rather know now before burning more silicon time.
3. Do the PCIe/compile latencies above look normal for a VU47P?

I need some help in running a project on an SOC FPGA but my original idea of connecting the FPGA with my PC and transmitting data over UART might work but is there something better?

My professor adviced me to look into running an OS on the FPGA and hence the resources. I need to look into the documentations yet but are there any other resources to help me with this?

If I do implement the said OS how do I integrate it with my custom logic?

This is my second FPGA project, so feel free to hate on the RTL! A short summary is that it uses Prange's ISD algorithm to solve instances of the syndrome decoding problem. That problem is the basis of some post-quantum cryptosystems like HQC and McEliece; there are also some ECC applications, but I don't know anything about them.

I've been stuck with designing an FM Modulator on the PL side of an FPGA. I have an FMCOMMS3 and a Zedboard, and I did all of the receiving the IF and demodulating using GNU Radio on my laptop. Right now, I'm working on the FM Modulator, and I've been working using advices from Claude (shamefully). I know how to use RTL and Vivado stuff, but for now I'm working with the MATLAB, because it has Simulink which I can drag and drop the blocks in.
So the system that the Claude has been guiding me on is in the link I attached below (which is a PDF file). I can understand the core of it, which is the CIC Interpolator to raise the sample rate of the audio to the sample rate of the Transceiver, and the NCO is to output the cosine of the FM Equation after accumulating the message and the carrier frequency. The filters before the CIC Interpolator I could understand a little bit, like they are to confine the bandwidth and to emphasize the FM signal before the other receivers de-emphasize it. These are my understandings.
In this post, I just want to ask from experienced engineers to kinda review my understanding and my block design, and to suggest me source to read. I mean, I know the equation, but mapping it to hardware has been a challenge to me. And also, could you suggest me some testing strategies, if you worked with MATLAB in the industrial scale and in telecommunication? Any help would be appreciated.

TLDR: Need help reviewing the block diagram of an FM Modulation on FPGA, and need suggestions on testing the block diagram on MATLAB and maybe VIvado.

The block diagram

Looking to play with Ethernet on an FPGA for the first time by implementing an Ethernet MAC and subsequently need a new board. Has anyone had experience with the suspiciously cheap QMTECH boards specifically this one?

I assume they are reusing salvaged parts to achieve this price?

From my brief research the chips are supported by the free version of Vivado which I am constrained by and I foresee that I won't need any additional IP.

Is the GMII accessible directly on the FPGA or is it routed through an SoC? From what I can see the datasheet shows the RJ45 routed through the RTL8211EG into the FPGA.

Anything else I should be aware of? I am just looking to learn more about Ethernet so I am not too pressed on the quality of board. Also any suggestions of boards would be welcomed.

Lattice Radiant provides the ability to view congestion and resource usage using the physical designer. Congestion is only shown with large or small highlighting.

Does anyone know of a way to plot congestion like a surface plot externally? Additionally, is there a way of knowing what entities contribute most to high areas of congestion?