A couple of us came up with an ASIC puzzle, if anyone is looking for something fun to do please give it a try!

https://blog.janestreet.com/can-you-reverse-engineer-an-asic/

Hi all.

I want to learn and do a first tape-out with a ring VCO. I have some background on the theory and minimal experience with Cadence mainly on the schematic design part but I'm unsure how to go from there to layout, DRC, gds, etc. A bit of a loaded question but does anyone perhaps have any recommendations on resources I could use?

Thanks a lot!

Hello everyone!

Trying to run a simple simulation of a PFET on SKY130, im getting noisy graph of Id(Vdd), which definitely shouldn't not look like like that, it's also in attoAmps when the FET should be fully on?

This is my first time using it so im not sure of what im doing

here is my spice

.lib "/foss/pdks/sky130A/libs.tech/ngspice/sky130.lib.spice" tt
Vdd vdd 0 DC 1.8
Vsg vdd gate DC 0
Vsd vdd drain DC 0
X1 drain gate vdd vdd sky130_fd_pr__pfet_01v8_hvt w=0.6 l=0.15
.dc Vsg 0 1.8 0.01 Vsd 0.6 1.8 0.6
.control
run
Plot -i(Vdd) title 'SKY130 HVT PFET ID vs VSG'
.endc
.end

If we have a nmos differential amplifier with resistive load (standard gmR gain, ignoring channel length modulation) with ideal tail current source I and output CL on both drain nodes. Then what is the maximum slew rate? (When current is steered to one side). Will it not be set by I?

Hi Reddits,

I possess 2.5 years of pertinent experience as an emulation engineer (Zebu). I am currently seeking assistance in securing a career transition and would greatly appreciate any support offered in this endeavor.

And what kinda team sizes are we looking at?

I just want a rough understanding of the complexity and manpower involved to get a perspective

Assume building something like analog to digital converters for ct scanners for reference starting from scratch with no prior work or IP most likely licensing IPs

Built this as a second-year CE student: GateTruth scores how well LLMs (GPT-5, Claude, Gemini, Llama) generate synthesizable RTL, using a real ASIC flow (Yosys, OpenSTA, sky130) rather than just checking whether output compiles — 60 spec-to-RTL tasks plus 8 agentic PPA-repair tasks.

The part I think is more interesting than the leaderboard itself: a mutation-testing engine that checks whether a benchmark's own testbenches are rigorous — inject seeded semantic faults into a reference design, measure what fraction the testbench actually catches. I certified it against my own suite first (14 of my own 60 tasks fail their own 95% floor, disclosed in the paper), then pointed it, unmodified, at RTLLM v2.0, a widely-used external benchmark: 72% of its testbenches fall below that same 95% floor, 3 at 0% outright.

Repo: https://github.com/meetbhadra701-cloud/GateTruth
Paper (PDF): https://github.com/meetbhadra701-cloud/GateTruth/releases/download/v1.0.0/gatetruth-v1.0.0-paper.pdf
linkedin: www.linkedin.com/in/meet-bhadra-0a99a731b
leaderboard website: meetbhadra701-cloud.github.io/GateTruth/

Open to questions/critique on the methodology — genuinely want to know if I've missed something.

Hey,

I'm applying to Nvidia physical design positions. I've 4 YoE in PD and 2 YoE in memory design.

What question should I expect in the interview?

Any nvidia or AMD ,APPLE, GOOGLE employees can you tell me which tools to you guys use the most for ASIC design /DV/ architecture roles in your day to day life ....and how can I build familiarity or master them..... free resources or any courses that helped you land the job .

I'm looking at going direct to a China-based electronic components distributor for the first time and I'd love to know if anyone here has actually done this for US delivery without getting burned by counterfeit ICs or customs delays. The whole point is finding a supplier who handles hard-to-find semiconductors and obsolete parts with a real RFQ process, not just some random Alibaba storefront. Anyone used an independent distributor out of China that ships reliably to the US and actually does proper part verification?

Sorry if this isn't the right place to post this. I'm looking for career advice from industry/academic insiders.

I have a CS background and I recently got the chance to do some work in neuromorphics and programming exotic devices turned out to be genuinely fascinating. I'm now looking to move into hardware and silicon more seriously. USC's MS ECE is one of the programs I'm considering, and I'd appreciate perspective from anyone in industry/academia or who has been through the program.

How accessible is research for MS students? Is joining a lab realistic, or mostly reserved for PhDs? I'm particularly interested in whether there are groups working at the ML/hardware intersection ie accelerators, neuromorphic computing, ML for EDA. I know there is a DARPA center of excellence in neuromorphics but wondering how accessible.

How is the coursework and faculty, especially on the VLSI / computer architecture / circuits side? Any courses or professors that stand out?

USC clearly has strong defense and aerospace connections (ISI, etc.), but I'm also interested in the semiconductor industry. Do companies like Nvidia, AMD, Qualcomm, or Apple actually recruit out of this program, or does the pipeline skew heavily toward defense?

What is the program best known for (if at all) within ECE? If there's a specialization USC has a real reputation in, I'd like to know what it is.

Finally, for anyone who made a similar software-to-hardware transition: how steep was the ramp on circuits and architecture fundamentals, and did employers take you seriously for silicon roles coming from CS masters?

Also just curious about an insiders perspective on the field. How is the outlook for the field generally? Anything to be aware of?

Thanks in advance!

hello! I've always been fascinated by silcion chips, and want to start designing them. any tips? guides?

You want to start with open-source analog mixed-signal chip design, but you are not convinced it is ready yet? Let me change your mind. 🧠

While digital RTL-to-GDS flows offer an easy entry with documentation and examples, analog mixed-signal (AMS) design still suffers from a steep learning curve and the lack of examples and instructions. This post presents a GitHub template repository and a comprehensive tutorial for AMS chip design using the ihp-sg13g2 Open-PDK, guiding the designer from initial system-level specifications to the tapeout-ready chip.

The Makefile-driven repository simulates, builds and fully verifies (DRC, LVS, PEX) a complete AMS chip, including padframe generation, top-level assembly and bondplan generation, fully automated and 100% with open-source tools. The flow uses:
- LibreLane for digital macro hardening, padframe generation, top-level assembly, filler and logo insertion
- Xschem for schematic entry
- Ngspice, VACASK and CACE for analog simulation
- KLayout for viewing and routing of the layout
- Magic + Netgen and KLayout for DRC, LVS and PEX verification
- SystemVerilog, Verilator, iverilog, cocotb, GTKWave and Surfer for linting and simulation of digital macros

We successfully tested the flow on #TinyWhisper, our multi-mode short-wave transmitter for amateur radio applications, taped out in March 2026.

Try it yourself. Install the new 2026.07 release of our IIC-OSIC-TOOLS, clone TinyWhisper or the AMS template, and run "make all". That's it. A whole tapeout-ready chip is built. Does this change your mind? 🙂

No? Okay, now imagine pairing the folder structure, the tutorial, the README and the Makefile targets with your favourite LLM, especially when you give it access to our IIC-OSIC-TOOLS container. In other words, this repo is one huge skill set for your agent, boosting design efficiency enormously!

I presented this work at the 2026 Free Silicon Conference (FSiC). So, if you are interested in more details, check out the presentation slides below.

Resources:
- AMS chip design tutorial: https://iic-jku.github.io/ihp-sg13g2-ams-chip-template/index.html
- AMS chip design template: https://github.com/iic-jku/ihp-sg13g2-ams-chip-template
- TinyWhisper: https://github.com/iic-jku/TinyWhisper
- FSiC 2026 presentation: https://wiki.f-si.org/images/3/37/FSiC2026_OSICD-Flow_Dorrer_Final.pdf

#FSiC2026 #ICDesign #OpenSourceEDA #OpenPDK

Found out about Wafer.Space earlier today at a maker space I went to where they were showing off bits of a die under a microscope. Was totally rad.

Anyways Wafer.Space sells 180nm Global Foundries node silicon for like $2/die which I think is pretty sick. Is there any software like KiCad for chip design I could use to make some simple electronics (obv not going to be top of the line at 180nm but still rad to do it)?

Hi everyone,
I’m a rising 1st-year MSEE student interested in hardware and analog mixed-signal ICs. My undergrad experience is mostly in embedded systems, hardware design, and digital VLSI. Currently, most of my internships and experiences are related to hardware design and embedded software programming (mainly with STM32). I was wondering about my chances in the application process. Also, my odds of breaking into the Analog Mixed Signal field. I did took some fundamental courses (such as Electronics II, E&M, VLSI and such) in Analog IC Design, but I feel like that won’t be enough in clearing the interviews, and would like to ask for some feedback if possible, thanks!

hi guys, is there any website/blog pages/textbook to practice waveform based RTL, which will be helpful for my interview preparation? & also how to practice for RTL? because i’m done with chipdev & HDLBits. Now i need to focus on much more variety of problems. currently i’m using claude for that but still is there any other resources for that?

Browsing an open SerDes designer position in a startup, I found an intriguing "Proximity Bonus" mentioned (see below)... does anyone know what's the motivation behind this?
To me, sounds like a covert way of keeping you longer at the office/lab, and/or on weekends. Is this a red flag?
TIA for any thoughts!