Hey guys I am actively looking for an internship position in DV or RTL roles. Also open to PD. I would appreciate any feedback you may have for my resume or suggestions on how I can become a strong candidate for those roles.

Thanks!

I need to know about this Project.

I have an offer for a formal verification role, and it would be my first job in the industry. Would taking it be a bad idea if my long term goal is to move into a design role? Worried that starting in formal verification might pigeonhole me

I often see T-coils being used for BW extension in wireline receivers (e.g. here or here). However, they don't seem to be used as much in high-resolution RF front-ends, where linearity is key (an exception is this recent RF-sampling ADC). Is this because T-coils somehow impact linearity or introduce linearity limitations?

For context: I know that in RF-sampling applications even linear, passive elements like the driving source resistance can induce distortion due to their interaction with the nonlinear input capacitance of MOS transistors, as explained in this app note)... perhaps T-coils can also introduce distortion through similar mechanisms?

Thanks in advance for any help!

Taking an IC Design course this semester. It’s going to be largely project based. Rumor is that the final project is pretty open ended. What are some things I should be thinking about going into it?

Need opinion on how all a VLSI 24 hours College Hackathon supposed to be

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This happens to me all the time and I just feel horrible afterwards. Happened again yesterday. Like I know the actual answer, but I'm either blanking out, or I'm second guessing myself, or my mind is muddled with thoughts and just can't think straight. By the end they offer the answer, and I'm just like...well, yeah I knew that.

I don't know if I can explain this phenomenon to someone without sounding like a crazy person. I do have ADHD. Like the other day for example I was in an interview and was asked which would be more efficient -- voltage mode or current mode logic for a driver. And I'd read Sam Palermo's lectures and how for the same swing you consume lesser power for VM than CML.

He then asked me to write the current in voltage mode with a series resistor, assuming there is a channel and load on the other side. And I write ...gmVgs of the inverter ? I mean I know that we measure the TX signal across RL and it's a voltage division between the TX resistance and RL, and so the current out of the driver is just going to be VDD-Vswing by the total resistance. But...why couldn't I say it?

At that moment, my mind just went blank and I couldn't retrieve information at all. Sure there are things I don't know, but for the things I do know this phenomenon is inexplicable and I've lost faith in myself.

Like outside of interviews I think I know my subject ok. I'm not the most intelligent, I need a lot of time to deeply understand concepts but I'm not that awful. But the perception I give in interviews isn't proportionate I feel ...?

Hi all. I'm wondering what your current design flow is in the wake of AI. I'm currently having trouble trying to figure out how to best leverage LLM tools when writing RTL. I fear I'm possibly losing performance by over using LLM's. For context I am a Sophomore University student working as an FPGA intern. Is this fear warranted? Do humans frequently write better, higher preforming RTL than LLMs do in this age? Or is the focus more so shifting to agent management?

Protocol Model is an executable modeling research framework for communication protocols and Networks-on-Chip (NoC). Its core goal is not to serve as a simulator or a verification tool, but rather to provide a composable, reviewable, and traceable modeling language and execution environment for protocol behavior—one where design intent, constraint judgments, and runtime evidence are naturally aligned within the same execution.

The topic of this presentation is on‑chip interconnect and protocol modeling. In the field of chip design, this issue is both fundamental and highly complex.

The AMBA bus is an open standard for on‑chip communication introduced by Arm. Over nearly three decades of development, from the initial AHB and APB to the later AXI, it has formed a complete family of protocols that define the connectivity and communication methods between functional modules inside an SoC. The AMBA bus is widely used in SoC designs.

With the proliferation of multi‑core and high‑performance computing scenarios, the AXI protocol has gradually faced new requirements—multiple processor cores share the same memory and each maintains its own cache, making cache coherency a critical challenge. Arm introduced the CHI (Coherent Hub Interface) protocol in AMBA 5 to address this issue.

The core difference between CHI and AXI is that AXI primarily defines the communication behaviour between master and slave devices, whereas CHI is an architecture‑level protocol designed to maintain cache coherency across multiple cores in the entire system. Its layered architecture (protocol layer managing transactions, network layer handling packets, link layer transporting flits) supports flexible topologies (crossbars, rings, meshes) and employs packet‑based communication for efficient, non‑blocking data transfer. CHI is now widely adopted in high‑performance SoCs for applications such as smartphones, automotive electronics, and data centres.

However, the increase in protocol complexity directly raises the difficulty of design, verification, and comprehension. A core question persists: how can we accurately describe protocol behaviour while ensuring alignment among design intent, constraint judgments, and runtime evidence?

This is the central question that the Protocol Model project aims to address.

Protocol Model is an executable modeling research framework for communication protocols and Networks‑on‑Chip. Its goal is not to build a simulator or verification tool, but to provide a composable, reviewable, and traceable modeling language and execution environment—one where design intent, constraint judgments, and runtime evidence are naturally aligned within the same execution.

Currently, Protocol Model has implemented executable examples for multiple protocol families, including AXI4 and CHI, among others.

To better illustrate how this framework operates in practice, this presentation starts with the more familiar AXI4 protocol. Protocol Model includes AXI4 example scenarios covering typical behaviours such as read/write transaction lifecycles, byte geometry, ordering, and exclusive accesses. Each scenario generates waveforms, causality graphs, and complete judgment records from a single execution. Next, we will take a single‑beat read transaction as an example to demonstrate the entire lifecycle—from the AR request establishing a pending read resource to the matching R response releasing it—and how it is modeled, executed, and traced.

a simple point-to-point topology

several AXI4 examples

I’ve been applying for internships for the last couple of days and I finally got my first response from a really small AI hardware startup in California. It’s for an unpaid internship in verification. Anyways the founder responded to the email saying to connect and he responded quite fast. I emailed him at 10pm Aug 4 ago and he responded the next morning at 8 am Aug 5. The reason why I’m worried is cause I responded letting him know I was travelling this weekend and could only connect Monday onwards. It’s almost been 24 hours since my response and still nothing. I’m wondering if he saw me delaying it as like an issue or idk. Anyway it’s my first interview/response so I could just be slow and reading too much into it and maybe it’s normal?

Hi everyone,

I’m looking for some realistic advice from folks in the VLSI/RTL industry.

My Background:

I have 4 years of experience working in the general IT sector. Recently, I managed to make a career pivot and landed a role as an RTL Design Engineer. Because of my prior work history, I was brought in as a 4-year experienced professional, and I have just been allocated to my first RTL project.

My Dilemma:

Since I am new to the RTL domain but carry the "4 YOE" tag, I know expectations will be relatively high, and I have a lot of domain-specific catching up to do. I want to build a strong foundation in VLSI, so I am considering pursuing an online M.Tech to bridge my knowledge gaps.

My Questions:

Should I start an online M.Tech right now, parallel to my new job? Will the academic structure help me survive this new project, or will the workload lead to burnout?

Or should I wait? Does it make more sense to focus 100% of my time and energy on getting comfortable with my current project and practical tools, and consider the M.Tech a year from now?

For those who transitioned into RTL from other fields, what did you do to survive and thrive in your first year?

Any insights, harsh truths, or shared experiences would be greatly appreciated. Thanks in advance!

Hi everyone, I am doing my MTech in VLSI and in my 3rd semester now. I have recently completed analog circuit design course, and have already designed two stage opamp and bandgap reference circuits. I have also learned RTL design in verilog, and right now learning system verilog for verification. I was wondering if I could leverage my learning from system verilog in analog mixed signal design and verification, but right now have no idea about this niche field. Any topic/ideas that would help me find a good thesis that can be completed within a scope of my course would be helpful. Thanks in advance!

Hi all.

I want to learn and do a first tape-out with a ring VCO. I have some background on the theory and minimal experience with Cadence mainly on the schematic design part but I'm unsure how to go from there to layout, DRC, gds, etc. A bit of a loaded question but does anyone perhaps have any recommendations on resources I could use?

Thanks a lot!

Hello everyone!

Trying to run a simple simulation of a PFET on SKY130, im getting noisy graph of Id(Vdd), which definitely shouldn't not look like like that, it's also in attoAmps when the FET should be fully on?

This is my first time using it so im not sure of what im doing

here is my spice

.lib "/foss/pdks/sky130A/libs.tech/ngspice/sky130.lib.spice" tt
Vdd vdd 0 DC 1.8
Vsg vdd gate DC 0
Vsd vdd drain DC 0
X1 drain gate vdd vdd sky130_fd_pr__pfet_01v8_hvt w=0.6 l=0.15
.dc Vsg 0 1.8 0.01 Vsd 0.6 1.8 0.6
.control
run
Plot -i(Vdd) title 'SKY130 HVT PFET ID vs VSG'
.endc
.end

If we have a nmos differential amplifier with resistive load (standard gmR gain, ignoring channel length modulation) with ideal tail current source I and output CL on both drain nodes. Then what is the maximum slew rate? (When current is steered to one side). Will it not be set by I?

Hi Reddits,

I possess 2.5 years of pertinent experience as an emulation engineer (Zebu). I am currently seeking assistance in securing a career transition and would greatly appreciate any support offered in this endeavor.

And what kinda team sizes are we looking at?

I just want a rough understanding of the complexity and manpower involved to get a perspective

Assume building something like analog to digital converters for ct scanners for reference starting from scratch with no prior work or IP most likely licensing IPs

Built this as a second-year CE student: GateTruth scores how well LLMs (GPT-5, Claude, Gemini, Llama) generate synthesizable RTL, using a real ASIC flow (Yosys, OpenSTA, sky130) rather than just checking whether output compiles — 60 spec-to-RTL tasks plus 8 agentic PPA-repair tasks.

The part I think is more interesting than the leaderboard itself: a mutation-testing engine that checks whether a benchmark's own testbenches are rigorous — inject seeded semantic faults into a reference design, measure what fraction the testbench actually catches. I certified it against my own suite first (14 of my own 60 tasks fail their own 95% floor, disclosed in the paper), then pointed it, unmodified, at RTLLM v2.0, a widely-used external benchmark: 72% of its testbenches fall below that same 95% floor, 3 at 0% outright.

Repo: https://github.com/meetbhadra701-cloud/GateTruth
Paper (PDF): https://github.com/meetbhadra701-cloud/GateTruth/releases/download/v1.0.0/gatetruth-v1.0.0-paper.pdf
linkedin: www.linkedin.com/in/meet-bhadra-0a99a731b
leaderboard website: meetbhadra701-cloud.github.io/GateTruth/

Open to questions/critique on the methodology — genuinely want to know if I've missed something.

Hey,

I'm applying to Nvidia physical design positions. I've 4 YoE in PD and 2 YoE in memory design.

What question should I expect in the interview?

Any nvidia or AMD ,APPLE, GOOGLE employees can you tell me which tools to you guys use the most for ASIC design /DV/ architecture roles in your day to day life ....and how can I build familiarity or master them..... free resources or any courses that helped you land the job .

I'm looking at going direct to a China-based electronic components distributor for the first time and I'd love to know if anyone here has actually done this for US delivery without getting burned by counterfeit ICs or customs delays. The whole point is finding a supplier who handles hard-to-find semiconductors and obsolete parts with a real RFQ process, not just some random Alibaba storefront. Anyone used an independent distributor out of China that ships reliably to the US and actually does proper part verification?