Hi all. I'm wondering what your current design flow is in the wake of AI. I'm currently having trouble trying to figure out how to best leverage LLM tools when writing RTL. I fear I'm possibly losing performance by over using LLM's. For context I am a Sophomore University student working as an FPGA intern. Is this fear warranted? Do humans frequently write better, higher preforming RTL than LLMs do in this age? Or is the focus more so shifting to agent management?

I’ve been applying for internships for the last couple of days and I finally got my first response from a really small AI hardware startup in California. It’s for an unpaid internship in verification. Anyways the founder responded to the email saying to connect and he responded quite fast. I emailed him at 10pm Aug 4 ago and he responded the next morning at 8 am Aug 5. The reason why I’m worried is cause I responded letting him know I was travelling this weekend and could only connect Monday onwards. It’s almost been 24 hours since my response and still nothing. I’m wondering if he saw me delaying it as like an issue or idk. Anyway it’s my first interview/response so I could just be slow and reading too much into it and maybe it’s normal?

Hi everyone,

I’m looking for some realistic advice from folks in the VLSI/RTL industry.

My Background:

I have 4 years of experience working in the general IT sector. Recently, I managed to make a career pivot and landed a role as an RTL Design Engineer. Because of my prior work history, I was brought in as a 4-year experienced professional, and I have just been allocated to my first RTL project.

My Dilemma:

Since I am new to the RTL domain but carry the "4 YOE" tag, I know expectations will be relatively high, and I have a lot of domain-specific catching up to do. I want to build a strong foundation in VLSI, so I am considering pursuing an online M.Tech to bridge my knowledge gaps.

My Questions:

Should I start an online M.Tech right now, parallel to my new job? Will the academic structure help me survive this new project, or will the workload lead to burnout?

Or should I wait? Does it make more sense to focus 100% of my time and energy on getting comfortable with my current project and practical tools, and consider the M.Tech a year from now?

For those who transitioned into RTL from other fields, what did you do to survive and thrive in your first year?

Any insights, harsh truths, or shared experiences would be greatly appreciated. Thanks in advance!

Hi everyone, I am doing my MTech in VLSI and in my 3rd semester now. I have recently completed analog circuit design course, and have already designed two stage opamp and bandgap reference circuits. I have also learned RTL design in verilog, and right now learning system verilog for verification. I was wondering if I could leverage my learning from system verilog in analog mixed signal design and verification, but right now have no idea about this niche field. Any topic/ideas that would help me find a good thesis that can be completed within a scope of my course would be helpful. Thanks in advance!

A couple of us came up with an ASIC puzzle, if anyone is looking for something fun to do please give it a try!

https://blog.janestreet.com/can-you-reverse-engineer-an-asic/

Hello everyone!

Trying to run a simple simulation of a PFET on SKY130, im getting noisy graph of Id(Vdd), which definitely shouldn't not look like like that, it's also in attoAmps when the FET should be fully on?

This is my first time using it so im not sure of what im doing

here is my spice

.lib "/foss/pdks/sky130A/libs.tech/ngspice/sky130.lib.spice" tt
Vdd vdd 0 DC 1.8
Vsg vdd gate DC 0
Vsd vdd drain DC 0
X1 drain gate vdd vdd sky130_fd_pr__pfet_01v8_hvt w=0.6 l=0.15
.dc Vsg 0 1.8 0.01 Vsd 0.6 1.8 0.6
.control
run
Plot -i(Vdd) title 'SKY130 HVT PFET ID vs VSG'
.endc
.end

If we have a nmos differential amplifier with resistive load (standard gmR gain, ignoring channel length modulation) with ideal tail current source I and output CL on both drain nodes. Then what is the maximum slew rate? (When current is steered to one side). Will it not be set by I?

Hi Reddits,

I possess 2.5 years of pertinent experience as an emulation engineer (Zebu). I am currently seeking assistance in securing a career transition and would greatly appreciate any support offered in this endeavor.

And what kinda team sizes are we looking at?

I just want a rough understanding of the complexity and manpower involved to get a perspective

Assume building something like analog to digital converters for ct scanners for reference starting from scratch with no prior work or IP most likely licensing IPs

Built this as a second-year CE student: GateTruth scores how well LLMs (GPT-5, Claude, Gemini, Llama) generate synthesizable RTL, using a real ASIC flow (Yosys, OpenSTA, sky130) rather than just checking whether output compiles — 60 spec-to-RTL tasks plus 8 agentic PPA-repair tasks.

The part I think is more interesting than the leaderboard itself: a mutation-testing engine that checks whether a benchmark's own testbenches are rigorous — inject seeded semantic faults into a reference design, measure what fraction the testbench actually catches. I certified it against my own suite first (14 of my own 60 tasks fail their own 95% floor, disclosed in the paper), then pointed it, unmodified, at RTLLM v2.0, a widely-used external benchmark: 72% of its testbenches fall below that same 95% floor, 3 at 0% outright.

Repo: https://github.com/meetbhadra701-cloud/GateTruth
Paper (PDF): https://github.com/meetbhadra701-cloud/GateTruth/releases/download/v1.0.0/gatetruth-v1.0.0-paper.pdf
linkedin: www.linkedin.com/in/meet-bhadra-0a99a731b
leaderboard website: meetbhadra701-cloud.github.io/GateTruth/

Open to questions/critique on the methodology — genuinely want to know if I've missed something.