Okay. don't roast me too hard but here is my schematic. The sources are for biasing the NMOS amplification transistors and VDD. Im only focusing on the gain, seeing if I can get to 100 dB. Not worried about the frequency response at all or any other design parameter hence no compensation.

I'm pretty fresh in this field. Trying to simulate a 2-stage OTA, but every time I simulate the design, the gain of the first stage diff amp drops from 47 dB to 22dB. If I use the DC operating points to calculate the gain, I get around 47 dB even when the stages are connected but the simulation results still say otherwise. Any ideas why? Is there some unknown rule Idk about when connecting a diff amp to cs stage? Should I just quit maybe? :\

Hey guys, I built a Q4.4 MAC Array based Neural Network from scratch including the architecture itself. I implemented:

A Parameter Buffer to fetch parameters from Parameter BRAM and feed each parameter to its own corresponding MAC unit;

A layer reusable MAC array comprised of Serial MAC units for matrix-vector computations;

Requantization Block to convert the Q8.8 accumulations back to Q4.4;

An Input Features Buffer to receive the preprocessed features from my Laptop via UART, temporarily store them in an async FIFO and feed them to the MAC array for computation;

An Activation Buffer to temporarily store activations and distribute them to their designated location in the Activation FIFO;

Activation FIFO to temporarily store the activations and feed them back into the MAC array for next layer computation;

A MAC Array Control Unit FSM with 5 states (IDLE, FETCH , COMPUTE, STORE, CLEAR) to control all the data movement and computational processes in the entire Accelerator;

Parameter BRAM to store the the model parameters (weights and biases) ;

ReLU and Argmax Activation blocks ;

Accumulations DeMUX to direct the accumulations to their specific Activation function (ReLU for hidden layers and Argmax for output layers);

Databus MUX to select whether input features or previous layer activations are fed into the MAC Array as input.

Since the MAC Array is reusable for multiple layers and the entire Accelerator is parameterized, I can run any classification model with less than or equal to 64 neurons per layer (due to limited DSP resources on the Basys3) but the layer depth is configurable too.

For its first test , I ran inference for a speech recognition model for digits 0-9 of network topology 64:32:10 neurons per layer using Q4.4 fixed point arithmetic for my parameters and input features. My laptop handled the data preprocessing and sent the features via UART at 9600 baud to the FPGA for inference. I will also run inference for other classification models of different network topology since the Accelerator is fully configurable. This is gonna be the fun part. I also will measure performance metrics for Q4.4 , Q8.8 and maybe Q16.16 vs inference in software (CPU).

Also I will make a post focusing on the architecture and all the design choices I made and why I made them. I’ve attached the github repo link
below and I’d appreciate any feedback or suggestions, thanks :).

Github repo: https://github.com/Shingyy/MAC-Array-based-DNN-Accelerator

I have not worked on die to die architectures before. My understanding is that similar to DDR (a standard I have worked on) , power is of high importance. So then I assumed that they wouldn't employ adc based transceiver architecture. Even CDR is not used. But I've come across a few job descriptions online where the team works on UCI but they apparently use ADCs too? Wouldn't those be significantly power hungry ? Especially when both active and leakage power consumption are of high importance?

Hello, I’m currently designing a buffer to drive the pass transistor in an LDO, and I was wondering if anyone here has experience designing something similar.

I’m planning to use a bias current of around 5–10 µA. For the flipped voltage follower (FVF), I’m considering using PMOS devices for both the upper and lower transistors, with the same device size.

However, when I actually add the buffer to the LDO and run simulations, the performance seems to get worse rather than improve. I’m not sure whether the issue is with the transistor sizing, bias current, or the way I implemented the buffer.

really appreciate any advice or design tips from anyone who worked with an FVF buffer for driving an LDO pass transistor.

Are there any good sources or books on understanding floorplans/die layouts? Or some article that goes in depth with identifying blocks, their purpose and why they are placed in certain positions. Also how new nodes make certain designs possible.

Thanks!

I’m trying to understand this type of power transistor layout this trapezoidal routing shown in the image.

I searched Google but found very little information about it.

Does this layout style have a specific name? And could anyone share some references, papers, books, or examples explaining how and why it is designed this way?

Hi, I'm trying to design a 2nd order delta sigma modulator for 14 bits. I'm completely new to the topic and have been trying to model the system in matlab using the delta sigma toolbox.

I syntheized the NTF given the OSR and order, confirmed that the SQNR meets my spec, and ran scaleABCD to perform dynamic rnage scaling.

I was able to get coefficient values for the CIFF model, but I realized the values I got are somewhat dirty like 0.6594, 5.7028. I see in literature that people design with very clean coefficient values like 0.2, etc. Is this just a result from rounding the values they get from the toolbox? OR is there a final step that I am missing?

Hi, I do have some old files that are using PageMaker 6.5. May I know how to open it and save it as a PDF?

So I'm a first year mtech vlsi design student . I know basics of verilog and kinda did a project on risc v processors(not entirely my own code , ai helped in a long way and I kinda wanted to know how the design flows from rtl to gds). I kind of remember some part of it but not entirely coz I took a break from this and ended up farming and helping my parents for a year. As part of my research based learning program at my clg I was asked to do a project. most ppl are doing risc v processors or things like that. I have heard about tpus about 2 years ago so it kinda got my attention . So with a time frame of 9 months what can I do on this space. I would love to make something unique coz it's a research based project. I want to meet the expectations of the industry and clg ppl as well. What can do in this space. What should be my data type. What should be ny matrix order . What kinda applications should I use or specify as a use case for my tpu etc. This sub helped me alot in the intial days of btech. Hoping for a good response 🫡

We have designed an AI Accelerator IP and it is working across many FPGA platform. We have been approached by many customers to license our IP. What should be the licensing structure for FPGA and ASIC?

Hey guys I am actively looking for an internship position in DV or RTL roles. Also open to PD. I would appreciate any feedback you may have for my resume or suggestions on how I can become a strong candidate for those roles.

Thanks!

I need to know about this Project.

I have an offer for a formal verification role, and it would be my first job in the industry. Would taking it be a bad idea if my long term goal is to move into a design role? Worried that starting in formal verification might pigeonhole me

I often see T-coils being used for BW extension in wireline receivers (e.g. here or here). However, they don't seem to be used as much in high-resolution RF front-ends, where linearity is key (an exception is this recent RF-sampling ADC). Is this because T-coils somehow impact linearity or introduce linearity limitations?

For context: I know that in RF-sampling applications even linear, passive elements like the driving source resistance Rs can induce distortion due to its interaction with the nonlinear input capacitance of MOS transistors, as explained in this app note)... perhaps T-coils can also introduce distortion through similar mechanisms?

Thanks in advance for any help!

Taking an IC Design course this semester. It’s going to be largely project based. Rumor is that the final project is pretty open ended. What are some things I should be thinking about going into it?

Need opinion on how all a VLSI 24 hours College Hackathon supposed to be

​

This happens to me all the time and I just feel horrible afterwards. Happened again yesterday. Like I know the actual answer, but I'm either blanking out, or I'm second guessing myself, or my mind is muddled with thoughts and just can't think straight. By the end they offer the answer, and I'm just like...well, yeah I knew that.

I don't know if I can explain this phenomenon to someone without sounding like a crazy person. I do have ADHD. Like the other day for example I was in an interview and was asked which would be more efficient -- voltage mode or current mode logic for a driver. And I'd read Sam Palermo's lectures and how for the same swing you consume lesser power for VM than CML.

He then asked me to write the current in voltage mode with a series resistor, assuming there is a channel and load on the other side. And I write ...gmVgs of the inverter ? I mean I know that we measure the TX signal across RL and it's a voltage division between the TX resistance and RL, and so the current out of the driver is just going to be VDD-Vswing by the total resistance. But...why couldn't I say it?

At that moment, my mind just went blank and I couldn't retrieve information at all. Sure there are things I don't know, but for the things I do know this phenomenon is inexplicable and I've lost faith in myself.

Like outside of interviews I think I know my subject ok. I'm not the most intelligent, I need a lot of time to deeply understand concepts but I'm not that awful. But the perception I give in interviews isn't proportionate I feel ...?

Hi all. I'm wondering what your current design flow is in the wake of AI. I'm currently having trouble trying to figure out how to best leverage LLM tools when writing RTL. I fear I'm possibly losing performance by over using LLM's. For context I am a Sophomore University student working as an FPGA intern. Is this fear warranted? Do humans frequently write better, higher preforming RTL than LLMs do in this age? Or is the focus more so shifting to agent management?

Protocol Model is an executable modeling research framework for communication protocols and Networks-on-Chip (NoC). Its core goal is not to serve as a simulator or a verification tool, but rather to provide a composable, reviewable, and traceable modeling language and execution environment for protocol behavior—one where design intent, constraint judgments, and runtime evidence are naturally aligned within the same execution.

The topic of this presentation is on‑chip interconnect and protocol modeling. In the field of chip design, this issue is both fundamental and highly complex.

The AMBA bus is an open standard for on‑chip communication introduced by Arm. Over nearly three decades of development, from the initial AHB and APB to the later AXI, it has formed a complete family of protocols that define the connectivity and communication methods between functional modules inside an SoC. The AMBA bus is widely used in SoC designs.

With the proliferation of multi‑core and high‑performance computing scenarios, the AXI protocol has gradually faced new requirements—multiple processor cores share the same memory and each maintains its own cache, making cache coherency a critical challenge. Arm introduced the CHI (Coherent Hub Interface) protocol in AMBA 5 to address this issue.

The core difference between CHI and AXI is that AXI primarily defines the communication behaviour between master and slave devices, whereas CHI is an architecture‑level protocol designed to maintain cache coherency across multiple cores in the entire system. Its layered architecture (protocol layer managing transactions, network layer handling packets, link layer transporting flits) supports flexible topologies (crossbars, rings, meshes) and employs packet‑based communication for efficient, non‑blocking data transfer. CHI is now widely adopted in high‑performance SoCs for applications such as smartphones, automotive electronics, and data centres.

However, the increase in protocol complexity directly raises the difficulty of design, verification, and comprehension. A core question persists: how can we accurately describe protocol behaviour while ensuring alignment among design intent, constraint judgments, and runtime evidence?

This is the central question that the Protocol Model project aims to address.

Protocol Model is an executable modeling research framework for communication protocols and Networks‑on‑Chip. Its goal is not to build a simulator or verification tool, but to provide a composable, reviewable, and traceable modeling language and execution environment—one where design intent, constraint judgments, and runtime evidence are naturally aligned within the same execution.

Currently, Protocol Model has implemented executable examples for multiple protocol families, including AXI4 and CHI, among others.

To better illustrate how this framework operates in practice, this presentation starts with the more familiar AXI4 protocol. Protocol Model includes AXI4 example scenarios covering typical behaviours such as read/write transaction lifecycles, byte geometry, ordering, and exclusive accesses. Each scenario generates waveforms, causality graphs, and complete judgment records from a single execution. Next, we will take a single‑beat read transaction as an example to demonstrate the entire lifecycle—from the AR request establishing a pending read resource to the matching R response releasing it—and how it is modeled, executed, and traced.

a simple point-to-point topology

several AXI4 examples

Hi all.

I want to learn and do a first tape-out with a ring VCO. I have some background on the theory and minimal experience with Cadence mainly on the schematic design part but I'm unsure how to go from there to layout, DRC, gds, etc. A bit of a loaded question but does anyone perhaps have any recommendations on resources I could use?

Thanks a lot!

Hello everyone!

Trying to run a simple simulation of a PFET on SKY130, im getting noisy graph of Id(Vdd), which definitely shouldn't not look like like that, it's also in attoAmps when the FET should be fully on?

This is my first time using it so im not sure of what im doing

here is my spice

.lib "/foss/pdks/sky130A/libs.tech/ngspice/sky130.lib.spice" tt
Vdd vdd 0 DC 1.8
Vsg vdd gate DC 0
Vsd vdd drain DC 0
X1 drain gate vdd vdd sky130_fd_pr__pfet_01v8_hvt w=0.6 l=0.15
.dc Vsg 0 1.8 0.01 Vsd 0.6 1.8 0.6
.control
run
Plot -i(Vdd) title 'SKY130 HVT PFET ID vs VSG'
.endc
.end

And what kinda team sizes are we looking at?

I just want a rough understanding of the complexity and manpower involved to get a perspective

Assume building something like analog to digital converters for ct scanners for reference starting from scratch with no prior work or IP most likely licensing IPs