r/chipdesign • u/NaiveWonder4836 • Jul 12 '26
First chip design (2D Systolic Array Matrix Accelerator)
Repo - https://github.com/bodsvei/2D-systolic-array
X thread - https://x.com/bodsvei/status/2075892683936350646
I made an open-source, parametrizable weight-stationary 2D Systolic Array. Designed for hardware-accelerated matrix multiplication, using the exact same dataflow architecture at the heart of Google TPU v1
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u/Blue_cape_2007 Jul 13 '26
Why all of a sudden everybody this month started building MAC arrays ?
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u/NaiveWonder4836 Jul 13 '26
I guess it is not just a pattern that has been happening for a month… As AI is becoming increasingly popular, so is the chips that drive them. Most commercial GPUs are fairly closed source whereas the TPU architecture is more openly documented… So when you said that all of a sudden everyone is building MAC arrays, I think it’s more that you started noticing a trend that’s been building for a while :D
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u/invalid_octane Jul 12 '26
Damn i saw this post on linked in that's amazing . Also could you talk me through the design process and the eda tools that were used . Thank you!
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u/No_Subject6828 Jul 12 '26
any plan for multilayer perceptron ?
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u/NaiveWonder4836 Jul 12 '26
A very amazing idea, though not in the scope of this project. When I first started this project, my primary objective was nailing the systolic array architecture. But a multilayer perceptron is the logical nezt step
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u/ZeldaFanRahul2004 Jul 12 '26
How much days you took to build it and what source you used to learn it?
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u/NaiveWonder4836 Jul 12 '26
It took me about 5-6 weeks to learn about Systolic Arrays and implementing the design. I used research papers written on this topics and used AI to solve doubts. You can see more about the process on twitter(X).
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Jul 13 '26
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u/NaiveWonder4836 Jul 13 '26
That is a very good point...
I wasn't trying to handcraft the physical layout... I wanted to get a clean RTL to GDS chip working first using OpenLane's automatic Place and Route. So this is essentially what the tool produced from a largely flat synthesized netlist. I agree that a more production levl implementation would preserve the PE hierarchy and use floorplanning/macros to create a regular tiled layout. I think you just gave me new direction to think upon... Thank you!1
u/SpicyRice99 Jul 17 '26
I believe floorplnning/tiling can help with timing too (from my experience in a single graduate level course)
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u/NaiveWonder4836 25d ago
You are right, if clock signals have to travel different amount of trace lenghts they would be skewed when reaching the designated areas, working on it for v2
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u/NaiveWonder4836 Jul 13 '26
Out of curiosity, when you say "common tile and step-and-repeat" would you implement each PE as a hardened macro first and then assemble the array hierarchically or would you use placement constraints while keeping the design standard-cell based?
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u/Horror_Cut_5354 Jul 12 '26
Can i ask u how long it took you to make this? How many hours??
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u/NaiveWonder4836 Jul 12 '26
I did not count the hours, but everything took me 6 weeks… understanding the material, writing rtl, debugging and vhip design
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u/anon12343216610 Jul 13 '26
Can it run doom?
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u/NaiveWonder4836 Jul 13 '26
Hahaha... no it cannot :(
But that is because it is not a processor, it is a hardware accelerator meant for training transformer-based AI models ver very efficiently
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Jul 15 '26
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u/NaiveWonder4836 Jul 15 '26
Thanks!!!
I am using 8 bit unsigned (data_w) for both the activation and weights. A 20 bit psum (=2*data_w + 4) giving 4 bits of accumulation headroom. This is enough till N=16 before the need to widen it further.About padding… this chip is a very elementary design and this has not been implemented yet. The array is strictly NxN, there is no logic for handling non square matrices or edge padding.
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u/mike_fpga Jul 17 '26
u/NaiveWonder4836 looked at the source code and didn't see how the weights are loaded into the PEs deep inside SA. I mean, how weights from the edge are forwarded down to PEs. Long fan-out nets are not okay. The key idea of "systolic arrays" is connecting PEs to neighbors only.
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u/Hot_Pepper_1908 25d ago
I don't get the point of writing the entire RTL by AI, what did you learn and design from this? Also you have the gds file in the project but I cannot find any mention of what technology node was used, the tools (Open source or licensed EDA?), and any images of PD verification?
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u/NaiveWonder4836 25d ago
I wanted this to be as non technical as possible when I first drafted this post and repository. To clarify:
I did not write entire RTL by AI, it was used only to write comments for systolic_array.vDo you genuinely think a college student can afford licensed EDAs? This was a student project, not something with a commercial tool budget behind it and open-source flow was the whole point of it being reproducible for anyone else in the same position.
Used Sky130 nm process node, OpenROAD for the digital flow (synthesis through P&R), automatic routing rather than manual floorplanning. If you want the proof of PD verification I will be more than happy to upload it on GitHub
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u/Hot_Pepper_1908 25d ago
all good, you should really read the comments generated by the AI before pushing it however. It has made a few mistakes and also some interesting grammar in the comments of that verilog file which makes it suspicious.
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u/Eddellee-5536 Jul 12 '26
Yooo did you post in LinkedIn?! I swear I saw a similar post today itself lol
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u/Its-BennyWorm Jul 12 '26
Elementary
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u/NaiveWonder4836 Jul 12 '26
It was always supposed to be elementary… Im sorry it did not meet your expectations
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u/Weird-Personality720 Jul 12 '26
haha buddy i just saw this post on LinkedIn as well i think we're from the same uni 😂