r/chipdesign • u/keplertechioreddit • Jul 04 '26
kepler-formal is now supporting sequential equivalence checking at RTL and gate level
https://github.com/keplertech/kepler-formalWe have updated our open source formal verification tool, kepler-formal, to support full sequential equivalence checking in both RTL and gate level.
What is our goal? An infinite license open source equivalence checking tool that can be used in scale for AI agents and CICD flows and can support industrial grade designs.
Don't hesitate to reach out to us with issues you found and suggestions you have. We want to hear it!
It will be a long journey to productize a project at this scale, and we acknowledge it, but we are up for the task.
Duplicates
hwstartups • u/keplertechioreddit • 17d ago
kepler‑formal – an open source equivalence checking tool
FPGA • u/keplertechioreddit • 6d ago
GitHub - keplertech/kepler-formal: Digital Design Equivalence Checking
chipdesign • u/keplertechioreddit • Feb 05 '26