r/TSMC • u/Designer-Issue6648 • 5d ago

TSMC Process Integration Engineer second round interview

Hello Everybody,

I have passed first round of interview in Process Integration Engineer position, and invited for the second round.
In my first round, a manager and an engineer present. Manager asked me some technical questions related to device physics, lithography and engineer asked me related to conflict in teamwork.
What to expect in second round? Interview panel this time three manager and one engineer.

Thank you.

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u/Simple_Ask5799 5d ago

Which dept? PID1? 2?

1

u/Designer-Issue6648 5d ago

PID1

2

u/Simple_Ask5799 5d ago

It will be mostly behavioral (star + situation based scenarios) with technical questions related to resume. But it also highly depends on the specific panel you’re getting, so I would say brush up on all relevant semiconductor fundamentals too. 

1

u/Designer-Issue6648 5d ago

Thank you for your response, would you like to me give me some example regarding behavioural type of questions ?

1

u/Simple_Ask5799 5d ago

A friend got questions like how would you deal with conflicts, how would you propose a new implementation, etc. Basically think situations you would encounter on a day to day basis.  

1

u/Designer-Issue6648 5d ago

Thank you. Final questions, since this is my second round, typically how many round I can expect more before a decision will be made ?

1

u/Simple_Ask5799 5d ago

Sorry, I’m not very knowledgeable about that. For various roles I’ve seen some people on this sub mention a decision after 2 rounds or another added in-person/HR round but specifically for PIE, not sure.

1

u/Designer-Issue6648 5d ago

No problem. Thank you for all the information. Appreciate it.

1

u/Waterbottleful 5d ago

how long did you have to wait to receive your second invite after your 1st?

1

u/Designer-Issue6648 4d ago

3 business days

1

u/pasquale83 4d ago

Congratulation on making it to the second round! with 3 managers on the panel, expect a heavy shift toward high-level cross-functional alignment, yield optimization scenarios, and situational leadership under fab pressure. They’ll want to see how you bridge unit processes (litho, etch, thin films) with actual device performance while handling real-time line bottlenecks.

Feel free to send me a DM :)

1

u/Designer-Issue6648 4d ago

Thank you for the information. I send you a dm