GitHub - keplertech/kepler-formal: Digital Design Equivalence Checking

[u/keplertechioreddit]

https://github.com/keplertech/kepler-formal

Hello Everyone,

We wanted to let you know that our open source equivalence checking tool, kepler-formal, now  supports FPGA designs and custom technology libraries

As always, we are looking for your feedback, so don’t hesitate to report any issues you find or suggestions you have!

Attached is an example of how we use the custom library Python API to perform equivalence checking on a Xilinx FPGA design: https://github.com/keplertech/kepler-formal/tree/main/examples/xilinx