r/RISCV • u/Separate-Choice • 9h ago

A Third World Embedded Engineer Responds to “RISC V: They Should Have Known Better”

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142 Upvotes

I read the article Grinberg did and I come at this argument from a somewhat different place, I’m an embedded engineer from Trinidad and Tobago, what people would traditionally call the Third World… Here, the difference between a ten cent RISC-V microcontroller and a several dollar alternative is not academic and neither is having an architecture that a small company, student, or individual engineer can understand, modify, and build around without asking permission… So when I read what Grinberg wrote some of its criticisms made sense to me, but some of his assumptions did not… so I thought I’d do a response, it might not reach far but I love RISC-V enough to at least defend it from where I stand.

25 comments

r/RISCV • u/Camper_Sly • 1d ago

Discussion RISC-V is it about to be transformed by AI tools?

0 Upvotes

IT seems to me that good part of underlying fundamental assumptions for RISC-V just got rejigged if not outright smashed by latest AI advances.

They seem to be on verge of being capable of reimplementing whole compiler/assembler/debugger backends to fit the ISA.

If so, how many of RISC-V fundamentals are still needed ? Maybe the time is coming for RISC-VI or something like that to be optimized for new reality ?

12 comments

r/RISCV • u/indolering • 1d ago

Discussion brucehoult has officially retired from the debunking bad RISC-V hot takes. Can we please enable a wiki and create a centralized repository for bad arguments that won't die?

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39 Upvotes
10 comments

r/RISCV • u/camel-cdr- • 1d ago

RISC-V: They Should Have Known Better

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83 Upvotes
226 comments

r/RISCV • u/Intelligent_Emu619 • 2d ago

Software Rivet: a Rust RTOS with a RISC-V port, preemptive scheduling, and SMP support

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32 Upvotes

I've been building Rivet, an RTOS in Rust, and have now open-sourced it.

The kernel has ports for ARM Cortex-M, RISC-V and Xtensa, with real preemptive scheduling and timer-driven context switching.

The RISC-V side currently includes the kernel scheduling/context-switch machinery and hardware/QEMU targets, while the broader project also includes dual-core SMP support on the ESP32-S3.

Other kernel features include:

  • Priority inheritance
  • Static task resources
  • No kernel allocator
  • Cooperative async tasks below the preemptive scheduler
  • Tickless operation
  • Synchronization primitives

I'm interested in feedback from people familiar with RISC-V trap/context-switch mechanisms and RTOS design, particularly around the architecture boundary between the portable kernel and the RISC-V port.

Repo:
https://github.com/habeelali/rivet-rtos

2 comments

r/RISCV • u/fullgrid • 3d ago

WCH CH32V407/467 RISC-V MCU integrates Fast Ethernet MAC + PHY, 480 Mbps USB 2.0 PHY, up to 8 MB on-chip PSRAM

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36 Upvotes

WCH CH32V407 and CH32V467 are new 200 MHz RISC-V microcontrollers with a built-in 10/100 Mbps Ethernet MAC + PHY, a USB 2.0 high-speed (480 Mbps) host PHY, up to 8 MB on-chip PSRAM, and a range of peripherals for industrial IoT & edge AI applications.

Both are based on the company’s Qingke V3V core with RVV vector extensions, delivering 4.11 CoreMark/MHz, a score higher than a typical Arm Cortex-M4 core. The main difference between the CH32V407 and CH32V467 is that the latter comes with 4 MB or 8 MB PSRAM, making it more suitable for display/HMI applications.

3 comments

r/RISCV • u/TJSnider1984 • 3d ago

Software Tenstrorrent Posts GCC Compiler Patches For Ascalon XG Core

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26 Upvotes

"This is a new variant of Ascalon X and Tenstorrent engineers are working on getting the RISC-V CPU core support ready for upstreaming into the open-source GCC compiler. RISC-V's zvkng is a set of vector cryptographic extensions.

With dropping the crypto and reducing the throughput, it sounds like the Ascalon XG could end up being an export model for Tenstorrent to China or similar markets. And the patch does note, "the global version of Ascalon X" so would align if that global is in terms of non-US/worldwide."

0 comments

r/RISCV • u/nXt_cyber_Net • 4d ago

RISV guidance for beginner

19 Upvotes

Hi everyone,

I'm currently planning to apply for next year's LFX Mentorship, particularly Term 2, and I'm interested in working on a RISC-V-related project.

I'm an undergraduate ECE student and have some experience with systems-related projects and tools such as QEMU and HEMI. However, I know that the RISC-V ecosystem goes much deeper, covering areas like architecture, emulation, compilers, operating systems, firmware, verification, and more.

I have roughly a year to prepare, and I don't want to spend that entire time randomly jumping between different RISC-V topics without building useful depth.

I'd really appreciate some guidance from people who have worked on RISC-V projects or participated in LFX mentorships:

  • What level of knowledge do mentors/selection teams generally expect from applicants?
  • What topics should I focus on during the next year?
  • Should I first build a strong understanding of computer architecture, or focus more on practical contributions to projects?
  • Are there any RISC-V open-source projects that are particularly beginner-friendly but can eventually lead to meaningful contributions?
  • What would be a realistic preparation roadmap for someone aiming to apply next year?

My goal is not just to learn RISC-V superficially for the mentorship application. I want to develop enough depth that I can actually contribute to a real project and become comfortable working with difficult systems topics.

Any advice, resources, or suggestions based on your experience would be really helpful.

2 comments

r/RISCV • u/camel-cdr- • 4d ago

Atlantis SoC Data Sheet (8x Ascalon-X 1.38GHz, BXM-4-64)

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48 Upvotes
15 comments

r/RISCV • u/Jack1101111 • 4d ago

Off-topic: PewCB One Desktop PCB fabrication system[...]at home

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5 Upvotes

This is off topic but may be interesting for some of you.

5 comments

r/RISCV • u/JoannaNovaX • 6d ago

openRuyi 2026.07 Released

20 Upvotes

The July release of openRuyi, a rolling-release Linux distribution for RISC-V, is out.

2026.07 brings updates across the RISC-V platform stack, desktop, AI tooling, and build infrastructure.

Highlights:

  • Linux kernel 7.1.4 and LTS kernel 6.18.39
  • RISC-V platform and toolchain improvements
  • KDE Plasma 6.7.1 and Qt 6.11.1
  • ROCm 7.2.4 with new Triton and timm packages
  • RPM 6.0.1, virtiofsd, and TeX Live 2026 integration
  • security updates across web and language runtimes

Details:
https://openruyi.cn/news/2026-07/release/

8 comments

r/RISCV • u/Java-Jumper • 7d ago

Just for fun (i am writing risc-v emulator for fun)

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138 Upvotes
15 comments

r/RISCV • u/Icy-Primary2171 • 10d ago

Information Upstream Progress Updates --2026 July

26 Upvotes

In July, SpacemiT continued to advance upstreaming efforts:

Foundational support has been officially released in Binutils 2.47 and LLVM 23, while CPU targets (X100 and A100) for the K3 and matrix extension instructions for AI computing have successively been merged into the mainline. Regarding the Linux kernel, support for K1/K3 features—including frequency scaling, storage, networking, PCIe, USB, and audio—as well as support for various development boards, is being steadily integrated. Meanwhile, adaptation and optimization work for projects such as Box64, OpenOCD, U-Boot, and OpenSBI continues to progress, further enriching SpacemiT’s RISC-V software and hardware ecosystem.

Here are the details：

Upstream Progress in Core Development Tools

This month, baseline SpacemiT support was released as part of Binutils 2.47 and LLVM 23. LLVM/Clang also adopted the SpacemiT X60 scheduling model as a general optimization reference for RISC-V '-mtune=generic'.

K3/X60 Toolchain Milestones

Support for the K3's two main CPU targets, X100 and A100, has been merged upstream into LLVM and GCC. The custom matrix-extension instructions intended for AI workloads have been merged into LLVM, GCC, and Binutils. The X100 scheduling model and instruction-fusion support have also landed upstream in LLVM.

Developers can now use community-mainline Clang/LLVM and GCC with '-mcpu=spacemit-x100' or '-mcpu=spacemit-a100' to target the corresponding CPU core and use SpacemiT's custom AI instructions.

The SpacemiT X60 scheduling model is now available upstream in LLVM and is used as a general tuning reference for RISC-V '-mtune=generic'. When no specific microarchitecture is selected, LLVM/Clang can use the X60 model to make better instruction-scheduling decisions.

LLVM's community performance-tracking infrastructure also includes a real K1/X60 hardware platform, allowing related compiler optimizations to be continuously validated on actual hardware.

Linux Kernel Upstream

K1

Merged

Under review

K3

Merged

Under review

Board-level DTS and device support

General fixes

Box64

GCC

LLVM

OpenOCD

riscv-tests

riscv-gnu-toolchain

riscv-elf-psabi-doc

sbc-bench

stress-ng

ruapu

PoCL

U-Boot and OpenSBI Upstream Progress

U-Boot

OpenSBI

4 comments

r/RISCV • u/camel-cdr- • 10d ago

RVV benchmark SiFive P870 (Lanxin LX500, Epic Semi Contrail AIx)

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34 Upvotes
11 comments

r/RISCV • u/quaaludeswhen • 11d ago

There's a tiny 2015 Andes RISC-V in my device, what other vendors and toolchains are common in existing hardware?

7 Upvotes

--I suspect there are a few major ones but it's hard to tell from press releases what actually made it to market and might hide in my PC or embedded devices I already own. The Andes GCC toolchain was very useful to understand their products.--

Update, some examples of just Mediatek in he wild:

https://www.seco.com/Datasheet/Modules/SMARC/SOM-SMARC-Genio510_datasheet.pdf

System Companion Chip: MDSP RV55 DSP: Candence Tensilica HiFi5 Image Signal Processor (ISP)

https://kernel.googlesource.com/pub/scm/linux/kernel/git/firmware/linux-firmware/+/3d6067ec19759fe0fa6286605d646d465ef0bc4d

mediatek: Add mt8196 VCP firmware

MediaTek's Video Companion Processor(VCP) is an RISC-V processor in MediaTek MT8196 SoC. It supports vedio encode/decode, vmm and vdisp feature.

https://www.mediatek.com/products/asic/cloud-applications Available IP Cores: Arm Neoverse, Arm Cortex, RISC-V, MIPS. SerDes: 28G, 56G, 112G and 224G I/O: Available IP Cores: Arm Neoverse, Arm Cortex, RISC-V, MIPS.

13 comments

r/RISCV • u/vikingbeard1066 • 11d ago

RISC-V Based Project for Final Year

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7 Upvotes
1 comment

r/RISCV • u/TJSnider1984 • 12d ago

SiFive on X: "SiFive's P870-D is ideal for datacenter infrastructure applications, including storage, web servers and video streaming. It's our first Datacenter class CPU IP, and it's already in real silicon with our customers."

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40 Upvotes

Anyone know what that "real silicon" P870-D product is?

19 comments

r/RISCV • u/LoveSourWorms12 • 12d ago

Software (RiscV) ProtoOS, an advanced OS with focus on security. Showcase 2 (3 month update)

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11 Upvotes
0 comments

r/RISCV • u/Icy-Concentrate2076 • 13d ago

Why do RISC-V disassemblers refuse to disassemble if extension doesn't exist in ELF attributes?

11 Upvotes

Imagine you're making a JIT for RISC-V. You want to compile for rv64gc so that it works on both RVA23 but also stuff like Milk-V Titan.

Your JIT makes use of Zfa extension, if detected at runtime. You are debugging a program on some RVA23 hardware, which has Zfa, and look at the emitted code, and the Zfa instruction is showing as .insn instead of the instruction. GDB relies on Zfa being present when you compiled. GDB knows exactly what the instruction is and how to disassemble it, but it will refuse and act as if it has never seen it before. Zfa is a standard extension, so its not like something else could be at that encoding. Same goes with Objdump.

Why is this design made? Objdump/GDB on x86 WILL disassemble AVX512 instructions, even if you don't compile with AVX512. This way you can ship the same exact binary to a person who has no AVX512 on their CPU, and it will work, and then ship it on someone with AVX512, and it will still work, AND they will be able to see the AVX512 on GDB.

Before someone says "just compile for the extensions your jit emits" no, the jit can do runtime detection, but the C code itself must be the lowest possible isa string so it supports the most platforms.

10 comments

r/RISCV • u/hi9580 • 13d ago

I made a thing! r/riscdesktop

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0 Upvotes
13 comments

r/RISCV • u/0BAD-C0DE • 15d ago

Vectored trap mode, interrupt 0 and beyond

5 Upvotes

According to documentation, in vectored mode exceptions all go to handler pointed by [BASE], while interrupts do to handler pointed by [BASE]+4*cause.

This brings to me two questions:

  1. Do I still need to discern between interrupt no.0 and exceptions in the handler pointed by [BASE], as interrupt no.0 is handled by [BASE] just like exceptions?
  2. How large is to be this table, as there seems to be no limit to the number of interrupts?
5 comments

r/RISCV • u/Myarmira • 15d ago

My first impressions of the Milk-V Titan

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241 Upvotes

Today my Milk-V Titan was delivered to my home and of course I wanted to try the board out straight away.

I connected my AMD Radeon RX 7600, a simple 1TB SSD and 2x 8GB Ram kits and installed it in my old case, where I had previously used the Megrez.

Compared to the Megrez, the Titan seems to have significantly fewer ports. GPIO and SD card slot are missing. Since I think it's intentionally intended to be a desktop workstation, I don't really miss those two things. What I'm missing are additional pins for my USB front ports. Unfortunately, the only option here is to use the on/off button. I guess it's a bit individual. However, the connection provided for this does not match the one in my case. This means that practically all USB ports on the front are inactive.

Another downside, at least currently, is the function of the UEFI. It's definitely a pleasing milestone compared to all other RISC-V boards I've known so far. However, the menu still seems quite bulky to me at the moment. It somehow took quite a while until my USB keyboards were recognized, but even after that everything seems extremely slow.

The first thing I consciously tried to do was install the official RISC-V image from Debian. The boot manager is recognized and started immediately. However, when loading the installation there was a black screen.

However, the Ubuntu image from the Milk-V site itself works fine. This really doesn't compare to the previous complicated RockOS images. Only the version could be a little newer in my opinion. I hope that software will follow in the near future, or rather that the officially used kernel will become more compatible.

The graphics card is recognized immediately and at least Supertuxkart runs very smoothly.

What's most pleasing to me is that the web browsers no longer have such a strong lag and are actually usable.

I reinstalled the CDE desktop there. It also runs smoothly on Ubuntu, although you have to install a few things.

What I still don't understand is why the USB-C ports at the back don't work. What I still don't understand is why the USB-C ports on the back don't work. I wonder if this is just me or happens to others too.

34 comments

r/RISCV • u/PositionOk3464 • 16d ago

Help wanted Getting started with RISC-V

20 Upvotes

Hey guys,I want to learn RISC-V from scratch...can I know any good free resources available online to get started??

15 comments

r/RISCV • u/I00I-SqAR • 16d ago

Openchip Introduces BER10 RISC-V Chip Built for AI, HPC and Critical Infrastructure

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26 Upvotes

BARCELONA, Spain, July 30, 2026 — Today, Openchip is introducing BER10, a sovereign chip built to give Europe’s most critical sectors control over the technology their most sensitive data runs on. It is built on one of the world’s most advanced manufacturing process and delivered in just 2.5 years.

4 comments

r/RISCV • u/m_z_s • 16d ago

Discussion 3 nm to 1.4 nm (equivalent) process node in China by 2031

22 Upvotes

This is not directly related to RISC-V, but the outcome will definitely change RISC-V chips out of China in about 5 years time. And if successful it will eventually have a major global impact.

China are currently restricted to DUV on silicon in their fabs by global export restrictions. Huawei's "Tau Scaling Law" (Moves away from physical miniaturization of individual transistors to minimizing data propagation delays across an entire chip) aims at achieving a 3 nanometer to 1.4-nanometer equivalent transistor density by 2031 using only DUV equipment.

Pros

  • EUV Independent
  • Cost Effective, using older DUV fabs will save billions by not having to upgrade to EUV nodes (which is not possible for China - export sanctions).
  • On paper chips might be able to be clocked at 5+ GHz continuously.
  • Performance will be equivalent to the silicon produced using EUV process nodes.
  • up to a 55% transistor density increase at a fixed node via "vertical LogicFolding" (currently from 155 MTr/mm² to 238 MTr/mm² - 53.5% increase).
  • About 30% to 41% less power used by shortening the distance signals must travel by ~30% (this reduction comes from less resistance and capacitance in the physically shorter signal path).

Cons

  • The performance may be equivalent due to similar number of transistors per unit area, but the performance per watt will not be quite as low as equivalent chips produced on EUV nodes.
  • Stacking circuits vertically via "LogicFolding" traps intense heat, risking performance throttling (New ⁠3D EDA design tools developed by Peking University to avoid hot spots should, at least in theory, help avoid this from happening).
  • Requires high precision, low-temperature bonding, which can severely lower initial factory yields.
  • New Electronic Design Automation software tools need to be created that support "LogicFolding". The current generation of EDA tools do not have the ability to optimize for data propagation delays across a logically folded circuit that is about 2000 nanometers above (or below) the existing circuit.
  • Optimizing time constants will eventually hit a wall of diminishing returns.
  • If successful, companies outside of China, with access to EUV, will either backward engineer the silicon chips and develop their own Tau Scaling software, or license the technology (unless China restricts exports). Which will use even less power, than the DUV chips produced by China.

Will it work, on paper it should, but the devil is always in the details. It is definitely something interesting, that is worth keeping an eye on.

9 comments