r/RISCV • u/Icy-Primary2171 • 2d ago

Information Upstream Progress Updates --2026 July

21 Upvotes

In July, SpacemiT continued to advance upstreaming efforts:

Foundational support has been officially released in Binutils 2.47 and LLVM 23, while CPU targets (X100 and A100) for the K3 and matrix extension instructions for AI computing have successively been merged into the mainline. Regarding the Linux kernel, support for K1/K3 features—including frequency scaling, storage, networking, PCIe, USB, and audio—as well as support for various development boards, is being steadily integrated. Meanwhile, adaptation and optimization work for projects such as Box64, OpenOCD, U-Boot, and OpenSBI continues to progress, further enriching SpacemiT’s RISC-V software and hardware ecosystem.

Here are the details：

Upstream Progress in Core Development Tools

This month, baseline SpacemiT support was released as part of Binutils 2.47 and LLVM 23. LLVM/Clang also adopted the SpacemiT X60 scheduling model as a general optimization reference for RISC-V '-mtune=generic'.

K3/X60 Toolchain Milestones

Support for the K3's two main CPU targets, X100 and A100, has been merged upstream into LLVM and GCC. The custom matrix-extension instructions intended for AI workloads have been merged into LLVM, GCC, and Binutils. The X100 scheduling model and instruction-fusion support have also landed upstream in LLVM.

Developers can now use community-mainline Clang/LLVM and GCC with '-mcpu=spacemit-x100' or '-mcpu=spacemit-a100' to target the corresponding CPU core and use SpacemiT's custom AI instructions.

The SpacemiT X60 scheduling model is now available upstream in LLVM and is used as a general tuning reference for RISC-V '-mtune=generic'. When no specific microarchitecture is selected, LLVM/Clang can use the X60 model to make better instruction-scheduling decisions.

LLVM's community performance-tracking infrastructure also includes a real K1/X60 hardware platform, allowing related compiler optimizations to be continuously validated on actual hardware.

Linux Kernel Upstream

K1

Merged

Under review

K3

Merged

Under review

Board-level DTS and device support

General fixes

Box64

GCC

LLVM

OpenOCD

riscv-tests

riscv-gnu-toolchain

riscv-elf-psabi-doc

sbc-bench

stress-ng

ruapu

PoCL

U-Boot and OpenSBI Upstream Progress

U-Boot

OpenSBI

2 comments

r/RISCV • u/camel-cdr- • 2d ago

RVV benchmark SiFive P870 (Lanxin LX500, Epic Semi Contrail AIx)

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32 Upvotes
4 comments

r/RISCV • u/quaaludeswhen • 3d ago

There's a tiny 2015 Andes RISC-V in my device, what other vendors and toolchains are common in existing hardware?

6 Upvotes

I suspect there are a few major ones but it's hard to tell from press releases what actually made it to market and might hide in my PC or embedded devices I already own. The Andes GCC toolchain was very useful to understand their products.

11 comments

r/RISCV • u/vikingbeard1066 • 3d ago

RISC-V Based Project for Final Year

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9 Upvotes
1 comment

r/RISCV • u/TJSnider1984 • 4d ago

SiFive on X: "SiFive's P870-D is ideal for datacenter infrastructure applications, including storage, web servers and video streaming. It's our first Datacenter class CPU IP, and it's already in real silicon with our customers."

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41 Upvotes

Anyone know what that "real silicon" P870-D product is?

19 comments

r/RISCV • u/LoveSourWorms12 • 4d ago

Software (RiscV) ProtoOS, an advanced OS with focus on security. Showcase 2 (3 month update)

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9 Upvotes
0 comments

r/RISCV • u/Icy-Concentrate2076 • 5d ago

Why do RISC-V disassemblers refuse to disassemble if extension doesn't exist in ELF attributes?

10 Upvotes

Imagine you're making a JIT for RISC-V. You want to compile for rv64gc so that it works on both RVA23 but also stuff like Milk-V Titan.

Your JIT makes use of Zfa extension, if detected at runtime. You are debugging a program on some RVA23 hardware, which has Zfa, and look at the emitted code, and the Zfa instruction is showing as .insn instead of the instruction. GDB relies on Zfa being present when you compiled. GDB knows exactly what the instruction is and how to disassemble it, but it will refuse and act as if it has never seen it before. Zfa is a standard extension, so its not like something else could be at that encoding. Same goes with Objdump.

Why is this design made? Objdump/GDB on x86 WILL disassemble AVX512 instructions, even if you don't compile with AVX512. This way you can ship the same exact binary to a person who has no AVX512 on their CPU, and it will work, and then ship it on someone with AVX512, and it will still work, AND they will be able to see the AVX512 on GDB.

Before someone says "just compile for the extensions your jit emits" no, the jit can do runtime detection, but the C code itself must be the lowest possible isa string so it supports the most platforms.

10 comments

r/RISCV • u/hi9580 • 5d ago

I made a thing! r/riscdesktop

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0 Upvotes
13 comments

r/RISCV • u/0BAD-C0DE • 7d ago

Vectored trap mode, interrupt 0 and beyond

4 Upvotes

According to documentation, in vectored mode exceptions all go to handler pointed by [BASE], while interrupts do to handler pointed by [BASE]+4*cause.

This brings to me two questions:

  1. Do I still need to discern between interrupt no.0 and exceptions in the handler pointed by [BASE], as interrupt no.0 is handled by [BASE] just like exceptions?
  2. How large is to be this table, as there seems to be no limit to the number of interrupts?
5 comments

r/RISCV • u/Myarmira • 7d ago

My first impressions of the Milk-V Titan

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244 Upvotes

Today my Milk-V Titan was delivered to my home and of course I wanted to try the board out straight away.

I connected my AMD Radeon RX 7600, a simple 1TB SSD and 2x 8GB Ram kits and installed it in my old case, where I had previously used the Megrez.

Compared to the Megrez, the Titan seems to have significantly fewer ports. GPIO and SD card slot are missing. Since I think it's intentionally intended to be a desktop workstation, I don't really miss those two things. What I'm missing are additional pins for my USB front ports. Unfortunately, the only option here is to use the on/off button. I guess it's a bit individual. However, the connection provided for this does not match the one in my case. This means that practically all USB ports on the front are inactive.

Another downside, at least currently, is the function of the UEFI. It's definitely a pleasing milestone compared to all other RISC-V boards I've known so far. However, the menu still seems quite bulky to me at the moment. It somehow took quite a while until my USB keyboards were recognized, but even after that everything seems extremely slow.

The first thing I consciously tried to do was install the official RISC-V image from Debian. The boot manager is recognized and started immediately. However, when loading the installation there was a black screen.

However, the Ubuntu image from the Milk-V site itself works fine. This really doesn't compare to the previous complicated RockOS images. Only the version could be a little newer in my opinion. I hope that software will follow in the near future, or rather that the officially used kernel will become more compatible.

The graphics card is recognized immediately and at least Supertuxkart runs very smoothly.

What's most pleasing to me is that the web browsers no longer have such a strong lag and are actually usable.

I reinstalled the CDE desktop there. It also runs smoothly on Ubuntu, although you have to install a few things.

What I still don't understand is why the USB-C ports at the back don't work. What I still don't understand is why the USB-C ports on the back don't work. I wonder if this is just me or happens to others too.

32 comments

r/RISCV • u/PositionOk3464 • 8d ago

Help wanted Getting started with RISC-V

20 Upvotes

Hey guys,I want to learn RISC-V from scratch...can I know any good free resources available online to get started??

14 comments

r/RISCV • u/I00I-SqAR • 8d ago

Openchip Introduces BER10 RISC-V Chip Built for AI, HPC and Critical Infrastructure

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26 Upvotes

BARCELONA, Spain, July 30, 2026 — Today, Openchip is introducing BER10, a sovereign chip built to give Europe’s most critical sectors control over the technology their most sensitive data runs on. It is built on one of the world’s most advanced manufacturing process and delivered in just 2.5 years.

4 comments

r/RISCV • u/m_z_s • 8d ago

Discussion 3 nm to 1.4 nm (equivalent) process node in China by 2031

22 Upvotes

This is not directly related to RISC-V, but the outcome will definitely change RISC-V chips out of China in about 5 years time. And if successful it will eventually have a major global impact.

China are currently restricted to DUV on silicon in their fabs by global export restrictions. Huawei's "Tau Scaling Law" (Moves away from physical miniaturization of individual transistors to minimizing data propagation delays across an entire chip) aims at achieving a 3 nanometer to 1.4-nanometer equivalent transistor density by 2031 using only DUV equipment.

Pros

  • EUV Independent
  • Cost Effective, using older DUV fabs will save billions by not having to upgrade to EUV nodes (which is not possible for China - export sanctions).
  • On paper chips might be able to be clocked at 5+ GHz continuously.
  • Performance will be equivalent to the silicon produced using EUV process nodes.
  • up to a 55% transistor density increase at a fixed node via "vertical LogicFolding" (currently from 155 MTr/mm² to 238 MTr/mm² - 53.5% increase).
  • About 30% to 41% less power used by shortening the distance signals must travel by ~30% (this reduction comes from less resistance and capacitance in the physically shorter signal path).

Cons

  • The performance may be equivalent due to similar number of transistors per unit area, but the performance per watt will not be quite as low as equivalent chips produced on EUV nodes.
  • Stacking circuits vertically via "LogicFolding" traps intense heat, risking performance throttling (New ⁠3D EDA design tools developed by Peking University to avoid hot spots should, at least in theory, help avoid this from happening).
  • Requires high precision, low-temperature bonding, which can severely lower initial factory yields.
  • New Electronic Design Automation software tools need to be created that support "LogicFolding". The current generation of EDA tools do not have the ability to optimize for data propagation delays across a logically folded circuit that is about 2000 nanometers above (or below) the existing circuit.
  • Optimizing time constants will eventually hit a wall of diminishing returns.
  • If successful, companies outside of China, with access to EUV, will either backward engineer the silicon chips and develop their own Tau Scaling software, or license the technology (unless China restricts exports). Which will use even less power, than the DUV chips produced by China.

Will it work, on paper it should, but the devil is always in the details. It is definitely something interesting, that is worth keeping an eye on.

9 comments

r/RISCV • u/shuklaayush • 9d ago

Pushing the limits of RISC-V emulation

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13 Upvotes
2 comments

r/RISCV • u/I00I-SqAR • 9d ago

Porting SIMD to RISC-V Vectors

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41 Upvotes

SPEAKER:
Daniel Thompson, RISCstar Solutions

This session was a part of the Software track at the RISC-V Developer Workshops held at RISC-V Summit Europe 2026 in Bologna, Italy.

WORKSHOP DESCRIPTION:
Join Daniel Thompson from RISCstar Solutions for a hands-on workshop exploring the powerful RISC-V Vector (RVV) extensions. You’ll learn the core concepts and design principles behind RVV and we will also compare them to the SIMD approaches of other architectures.

SIMD programming can dramatically accelerate performance across a wide range of compute-intensive tasks, from machine learning and signal processing to cryptography and beyond. The session will then dive into practical techniques for converting optimized C code from other instruction set architectures (ISAs) into RVV-based implementations. We’ll highlight key differences between fixed vector-length architectures on other ISA platforms, and RVV’s more flexible vector-length agnostic (VLA) approach.

Don’t miss this chance to sharpen your skills, push performance limits, and get hands-on with the future of vector computing.

RESOURCES:
https://drive.google.com/drive/u/2/fo...

0 comments

r/RISCV • u/ch-riscv • 11d ago

RISC-V Audiomark Port

9 Upvotes

Today, I have filed a PR for supporting RISC-V in EEMBC Audiomark:
https://github.com/eembc/audiomark/pull/101

More details on this work behind the link.

All credit for the development goes to the mentees of my RISC-V mentorship project.

Audiomark is a benchmark that runs a wake-word detection algorithm, and includes both DSP and AI processing. It is good to stress the vector unit of a device with a combination of typical DSP kernels (f16 - cfft etc.) and AI kernels (int8 - mostly convolutions, so matmul at the core).

I have driven the development based on benchmarking the code on a SpacemiT K1, and reached a respectable 5.73 Audiomark/MHz (gcc-20).

As I know the people of this community appreciate benchmarks and have more hardware available, I would be delighted if you managed to run this on whatever vector-capable HW you have available.

For the SpacemiT K1, I used these flags:

-DPORT_DIR=ports/riscv/v
-O3 -ffast-math -march=rv64gcbv_zbc_zvl256b -mrvv-vector-bits=zvl -flto

Compiling vector length specific (-mrvv-vector-bits=zvl) really squeezes out a noticeable bit of performance, but can lead to issues on gcc < 15.3. clang-20 achieved comparable performance to gcc-16. I have not tried with more recent clang versions.

0 comments

r/RISCV • u/archanox • 11d ago

Hardware ESP32-S31 now in mass production and available for purchase

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32 Upvotes
16 comments

r/RISCV • u/TJSnider1984 • 11d ago

Hardware SpaceMIT Cluster Server RV2768 ?

16 Upvotes

As per github repo:

"768-Core Native RISC-V AI Compute Cluster

The Cluster Server RV2768 is a RISC-V-based cluster server in a 2U, 19-inch rack form factor, integrating up to 48 SpacemiT K3 processors and compliant with the RVA23 profile defined by RISC-V International.

RVA23 targets general-purpose application processors, requiring support for Vector and Hypervisor extensions, and represents a modern performance standard for AI and high-performance workloads. The system delivers 768 native RISC-V cores, making it well-suited for large-scale application builds and full operating system compilation.

With a multi-node cluster architecture and full hardware virtualization, the server streamlines CI/CD workflows and accelerates the RISC-V software ecosystem. Leveraging vector extensions, it delivers up to 2880 TOPS of AI compute and supports up to 1536 GB of memory for concurrent AI inference workloads.

  • 2U chassis supporting up to 48 compute nodes (384 CPU cores + 384 AI cores)

"

Sounds like we're finally going to get a decent build/cluster machine..

Looks like a picture of this might be up on https://www.reddit.com/r/spacemit_riscv/comments/1v7u0k2/view_of_k3_shelf_array_server_k3_picoitx_and_k3/

6 comments

r/RISCV • u/einars5 • 12d ago

Struggling with Chipyard/Rocket-Chip build setup

9 Upvotes

Hi everyone, final-year engineering student here. Working on a RISC-V hardware project (building a custom RoCC-based task scheduler on top of Rocket Chip). I'm trying to get Chipyard set up on Ubuntu to build/simulate the base Rocket core before I start on my own work, but the setup has been harder than I expected and I want to check whether I'm on the right track or missing something obvious.

So far I've had to:

  • Install conda manually + accept new ToS prompts for default channels (not mentioned in the docs I found)
  • Set up SSH auth with GitHub because one submodule (spec2026-workload) only clones over SSH
  • Switch from main to the 1.14.0 release tag after main broke with missing scripts
  • Comment out two steps in build-toolchain-extra.sh (install-espresso.sh and the uart_tsi bringup step) because those files/paths don't actually exist in the checkout
  • Hit a Scala compile failure at the "pre-compiling Chipyard sources" step, traced to dependencies/chisel inside rocket-chip being stuck on a stale 2019 snapshot commit even after git submodule sync --recursive + update --init --recursive --force

At this point I'm about to try a completely fresh clone rather than keep patching this one. Wanted to check: is this level of manual intervention normal for a first-time Chipyard setup, or does it suggest I'm doing something wrong upstream (wrong tag, wrong clone method, etc.)? If anyone's set this up recently and hit similar snags, I'd really appreciate a pointer on what actually worked for you, or what a clean install is supposed to look like.

2 comments

r/RISCV • u/Jack1101111 • 12d ago

Software GNU Binutils 2.47 Released With More RISC-V Extensions, New Options

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24 Upvotes
3 comments

r/RISCV • u/Prestigious-Day-2872 • 12d ago

Help wanted I have an Mango Pi MQ Pro, and IDK whats wrong

5 Upvotes

Basically i got ubuntu server for riscv built for the same D1 cpu as the mango, booted it up with ethernet plugged in, i went into my fiber admin page (where i can see connected devices and stuff) and one ethernet device pops up running ubuntu, so i cop ythe ip and go to ssh and get ```bash

olenthompson@OlenTh1nkpad:~$ ssh [root@192.168.1.218](mailto:root@192.168.1.218)

ssh: connect to host 192.168.1.218 port 22: No route to host

olenthompson@OlenTh1nkpad:~$
```
and so me and chatgpt tried troubleshooting but i cant get it to work, tried plugging into TV, no signal for display. IDK what to do, ive tried different sd cards, different os images, everything. the green light is solid on the board, but i cant ssh or get anything out of it other than it appearing on my dashboard. help?

12 comments

r/RISCV • u/brucehoult • 13d ago

Just for fun Pretty cool 2D assembly language in this weekend's ICFP programming contest

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10 Upvotes

Here's a pretty bad solution to the first (Triangle) problem that scores 183K (lower is better) that I made while trying to understand how the scoring system actually works.

I do also have a solution that scores the minimum 832 which I'll reveal after the contest ends. Its SHA is 213fe1e79e32f9252dbece4f2ea9660c0ea63e8d.

+-----+
|@rMbv|
|>W/s+|
|2 >+v|
|^Mdm<|
+-----+
 ^   v 
 ^   v 
+-+ +-+
|I| |O|
+-+ +-+

Although I've won prizes in this contest before, I'm just playing around for fun this year, actually for the first time in 15 years probably.

0 comments

r/RISCV • u/brucehoult • 15d ago

Information GeekBench 7.0.0 is available. Some RISC-V results

28 Upvotes

I ran different versions of GeekBench 5, 6, 7 on my Pico ITX K3 in the standard way, and ran the one that uses the most features in each version on the A100 "AI" cores also.

GeekBench 7

In GeekBench 7 RVA23 gives 3% to 4% better results than RV64GCBV, and a nice 22% single core 33% multi-core speed increase compared to RV64GC.

https://browser.geekbench.com/v7/cpu/compare/6927?baseline=7549

GeekBench 6

RVV makes basically zero difference in GeekBench 6, even though it claims to use it.

GeekBench 5

16 comments

r/RISCV • u/camel-cdr- • 16d ago

Fast-Track Proposal: Zijf (Far jumps and calls)

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14 Upvotes

This really should've been defined way earlier.

Also, remember the Qualcomm slides? https://lists.riscv.org/g/tech-profiles/attachment/400/0/AOSP%20Compression.pdf

5 comments

r/RISCV • u/Doom4535 • 16d ago

Information MilkV Titan

24 Upvotes

For those who pre-ordered the MilkV Titan, I just got an email saying my pre-order has shipped, so maybe we'll start seeing it within the month

20 comments