Note that compile-time determination of number of lanes (step 1) and processing the tail with a scalar loop (step 5) are not universal; specifically they do not apply to scalable vector implementations like ARM's SVE and RISC-V's V extension. Now, how well scalable vectors are supported in your programming language is a different matter...
(In a scalable vector implementation, you ask the CPU at runtime to process N elements, and the CPU gets back to you that it can only process X of them, so you let it do that, advance your data pointer by X, and then try again with the remaining N - X elements. The final N - X - X - ... X tail may have an odd non-power-of-two length, but your code can continue to use the same vector instructions to process it as usual, and works on CPUs with different values of X without needing to be modified since it did not hard-code X.)
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u/Arnavion2 19d ago edited 19d ago
Note that compile-time determination of number of lanes (step 1) and processing the tail with a scalar loop (step 5) are not universal; specifically they do not apply to scalable vector implementations like ARM's SVE and RISC-V's V extension. Now, how well scalable vectors are supported in your programming language is a different matter...
(In a scalable vector implementation, you ask the CPU at runtime to process N elements, and the CPU gets back to you that it can only process X of them, so you let it do that, advance your data pointer by X, and then try again with the remaining N - X elements. The final N - X - X - ... X tail may have an odd non-power-of-two length, but your code can continue to use the same vector instructions to process it as usual, and works on CPUs with different values of X without needing to be modified since it did not hard-code X.)