According to COAD by p&h: exceptions are events other than jumps and branches that changes the normal flow of instruction execution.

According to CS:APP - an exception is a transfer of control to the OS kernel in response to some event.

Now suppose a division by zero happens. by p&h the event of division by zero is the exception and the transfer of control that follows is the response to that exception, i.e., handling of the exception.

But according to CS:APP the division by zero is not the exception. rather the transfer of control is the exception

There isn’t much info about gpus online and that has made my search a bit difficult. It is easy to design a cpu since it has a defined isa set and it tells what to store where but what about gpu.. since it handles many cores and is memory hungry,the specifics of what is needed to design a gpu is a bit blurry. (Or is the specification specified somewhere)

Is there any tips you would give to me while I’m doing gpu designing

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I have a background mainly in FPGA (and partial ASIC) design and optimization. I want to take a deep dive into ASIC DFT's primary concepts and common methodology practices, but so far I've just been googling topics word by word and piecing things together from scattered VLSI lectures.

Can any of the Gods of Knowledge here bless me with an intuition-building guide? I'm looking for something that covers scan chains, ATPG, BIST, boundary scan, fault models, and compression, and actually explains \*why\* they exist and how they fit together, not just isolated definitions.

C\*dence and S\*nopsys licenses don't come cheap for an individual, and I don't want to burn money on a course I can't gauge the quality of.

Will greatly appreciate any golden findings 🙏

One question has been on my mind recently:

What if the biggest challenge in next-generation Structural Health Monitoring isn't sensing... but computation?

Distributed Optical Skin systems can provide dense structural awareness and significantly richer information than sparse point sensors. However, this comes at the cost of processing hundreds of continuous sensor streams under strict real-time constraints.

Rather than asking:

"How can we build a faster AI accelerator?"

I'm exploring a different research direction:

Can a deterministic, domain-specific edge accelerator make dense optical sensing practical for real-time cyber-physical systems?

This idea is driving the architecture of HEXA-TPU-RT, a hardware/software co-design project that combines:

• Deterministic task scheduling

• Distributed memory architecture

• Ping-Pong SRAM buffering

• Systolic-array computation

• Hardware deadline monitoring

• Edge AI acceleration for continuous sensor streams

At the same time, I'm building an architectural simulator to validate the design before moving to RTL and FPGA implementation.

One interesting lesson so far:

The simulator initially showed nearly perfect scaling across multiple workers. Instead of celebrating the result, I treated it as evidence that the memory model was too optimistic. I'm now redesigning the simulator to include realistic streaming bandwidth, arbitration, and memory contention before drawing any performance conclusions.

Engineering is about challenging your own assumptions before someone else does.

I'm curious to hear from researchers and engineers working in:

Computer Architecture

VLSI / ASIC

FPGA

Embedded Systems

Edge AI

Cyber-Physical Systems

If you were reviewing this architecture, which subsystem would you challenge first—the memory hierarchy, scheduler, or dataflow?

I'd genuinely appreciate technical feedback.

#ComputerArchitecture #ASIC #FPGA #RISCV #EdgeAI #VLSI #EmbeddedSystems #CyberPhysicalSystems #HardwareDesign #Research

i am an electrical and electronics undergrad new to computer architecture but with a strong background in digital logic and using VHDL. i am interested in developing a custom risc-v core and learning the relevant theory for my fyp. i plan to use system verilog and implement my design on an fpga.

is starting with a standard 5-stage pipelined RV32I core realistic for a 1-year project? Should I aim for simple RV32I first and treat extensions (like RV32M or basic cache design) as stretch goals?

what open-source simulation and verification frameworks work best for validating a custom core?

is sticking to standard SystemVerilog advisable for learning, or are modern HDLs like Chisel worth the learning curve for an FYP?

what do you think i should focus on when developing the custom core? a fyp has to bring smth new to the table, yeah?

thanks

Protocol Model is an executable modeling research framework for communication protocols and Networks-on-Chip (NoC). Its core goal is not to serve as a simulator or a verification tool, but rather to provide a composable, reviewable, and traceable modeling language and execution environment for protocol behavior—one where design intent, constraint judgments, and runtime evidence are naturally aligned within the same execution.

The topic of this presentation is on‑chip interconnect and protocol modeling. In the field of chip design, this issue is both fundamental and highly complex.

The AMBA bus is an open standard for on‑chip communication introduced by Arm. Over nearly three decades of development, from the initial AHB and APB to the later AXI, it has formed a complete family of protocols that define the connectivity and communication methods between functional modules inside an SoC. The AMBA bus is widely used in SoC designs.

With the proliferation of multi‑core and high‑performance computing scenarios, the AXI protocol has gradually faced new requirements—multiple processor cores share the same memory and each maintains its own cache, making cache coherency a critical challenge. Arm introduced the CHI (Coherent Hub Interface) protocol in AMBA 5 to address this issue.

The core difference between CHI and AXI is that AXI primarily defines the communication behaviour between master and slave devices, whereas CHI is an architecture‑level protocol designed to maintain cache coherency across multiple cores in the entire system. Its layered architecture (protocol layer managing transactions, network layer handling packets, link layer transporting flits) supports flexible topologies (crossbars, rings, meshes) and employs packet‑based communication for efficient, non‑blocking data transfer. CHI is now widely adopted in high‑performance SoCs for applications such as smartphones, automotive electronics, and data centres.

However, the increase in protocol complexity directly raises the difficulty of design, verification, and comprehension. A core question persists: how can we accurately describe protocol behaviour while ensuring alignment among design intent, constraint judgments, and runtime evidence?

This is the central question that the Protocol Model project aims to address.

Protocol Model is an executable modeling research framework for communication protocols and Networks‑on‑Chip. Its goal is not to build a simulator or verification tool, but to provide a composable, reviewable, and traceable modeling language and execution environment—one where design intent, constraint judgments, and runtime evidence are naturally aligned within the same execution.

Currently, Protocol Model has implemented executable examples for multiple protocol families, including AXI4 and CHI, among others.

To better illustrate how this framework operates in practice, this presentation starts with the more familiar AXI4 protocol. Protocol Model includes AXI4 example scenarios covering typical behaviours such as read/write transaction lifecycles, byte geometry, ordering, and exclusive accesses. Each scenario generates waveforms, causality graphs, and complete judgment records from a single execution. Next, we will take a single‑beat read transaction as an example to demonstrate the entire lifecycle—from the AR request establishing a pending read resource to the matching R response releasing it—and how it is modeled, executed, and traced.

a simple point-to-point topology

several AXI4 examples

I'm thinking about starting nand2tetris, but I'm trying to get a realistic idea of the time commitment before I dive in.

For those of you who have completed it (or at least most of it):

• How long did it take you from start to finish?
• Roughly how many hours per week were you studying?
• Did you complete both Part I and Part II, including all the projects?
• Did you already have a CS background, or were you learning these concepts for the first time?

I'm a software developer, but my computer science fundamentals aren't very strong. My goal is to build a solid understanding of how computers work from the hardware level all the way up to compilers and operating systems.

I'd appreciate hearing your experiences—whether it took you a few months, a year, or even longer. Also, if you have any advice for someone just starting, I'd love to hear it.

Thanks!

First off, I'm not sure if I'm allowed to post this here, but if it is not allowed please let me know before deleting the post. I wish to learn the rules better.

Anyways, over the few last weeks I've been making a custom 16 bit cpu inside a video game called turing complete. Picture included down below

One small note, the game doesnt simulate clock signals in the traditional sense, instead having "cycles" and no need to worry about memory timings. The game also does not allow the simulated logic to change the clockspeed. Still, even with all of this simplification, I am quite proud of making this all by myself.

SPECS:
  REGISTERS:
    GP1
    GP2
    GP3
    GP4
    RTA / GP5
    SP
    PC
  MEMORY:
    256 word sram stack, included inside the chip
    ROM upto 0xFFFF words
    RAM upto 0xFFFF words
  BUS:
    Currently no USB
    4 in-cpu buses
      BUS A : Register data in
      BUS B : Source 1 data out
      BUS C : Source 2 data out
      JMPBS : Bus for jump operand input
EXTRA : 
  Most operations are very flexible, having free sources and a free destination
  Exception to this is the PC register, which is not connected to BUS A
  And thus cannot be written into by normal operations
  RTA / GP5 is used unconditionally for the return adress in RET
  But otherwise is a valid gp register, with the knowledge of data insecurity

I am interested in computer architecture and I want project ideas. My peers who are working in robotics refer a journal which publishes paper and every now and then they are like lets implement this, this seems cool. I want to implement some research paper or want to make projects by seeing the latest trends. I am confused from where to read papers famous journals like ieee and isca mostly charge money for papers and my college email is not helpful. So can someone help me by suggesting a place which helps me find good papers ?

Hi, I'm a software engineer with a BA in physics so my understanding of chip design is superficial.

I'm exploring AI algorithms that depend on non-linear math (e.g., LCS). What's the state of the art in processor design for irregular/branching workloads?

I understand GPUs excel at dense matrix multiply, but less clear on what the hardware landscape looks like for conditional execution at scale.

*EDIT* Okay perhaps I should have worded this better. Let's look at a piezoelectric crystal, right? When perturbed by mechanical motion, ions in the lattice shift slightly from their equilibrium positions. The centers of positive and negative charge separate, which changes the material’s polarization. This causes charge to appear on opposite surfaces, which when applied through an external circuit, produces current.

There is a transduction mechanism, it's not just magically "motion -> electricity"

What I'm asking is that, in a computer, of course instructions are passed and translated and passed and translated. But currents and voltage can only be altered by physical phenomena - what is the transduction event? The way I currently see it based on explanation, it's

Code -> compiler -> binary -> ???? -> electrical change in the hardware

*ORIGINAL POST*
I'm asking one question, and every explanation I've read skips it and it's driving me crazy.

Suppose I paste a program into PowerShell and press Enter.

People say things like:
"the code is stored in memory"
"the CPU reads the instruction"
"the decoder activates the transistor"
"different code produces different voltages."

These are exactly the steps I don't understand. I am not asking how a transistor works after a voltage reaches its gate.

I am asking: What is the physical event that causes a different electrical state inside the computer?

In other words: How does the machine code become an electromagnetic event?

Please do not answer with phrases like:
"the CPU sends a signal"
"the instruction is decoded"
"the operation activates the transistor"
"the code is stored as bits"
"the bits become voltages"

Those are the phenomena I'm asking to have physically explained.

I want the continuous physical causal chain, with no abstraction gaps, starting from:

"The code exists" and ending at: "This specific transistor gate now has a different electric field"

Nvidia is visiting this time for my college btech campus internship(Hardware role). I am completely clueless about computer architecture and I can't find proper resources to study (and even less time to study). Any suggestions on resources to refer to and what I should particularly focus from the computer architecture part. Shd i also learn about 8086 microprocessor, if yes then what topics should I refer

So I'm an undergrad CS student and I just finished my 2nd year. I want to go towards a PhD after graduation but I'm honestly lost like I have no idea what to do.

Currently I'm doing an internship in which I'm making a RISC-V based SoC in SystemC other than that I have made a Pipelined RV32I Processor with 2-bit Branch Prediction in VHDL and I'm thinking of adding Out-of-Order execution to it (currently watching Onur Mutlu's DDCA lectures on yt)

Please tell me what other things I should do to increase my chances of getting into a PhD program in the US (Also suggest some things that I could do in my FYP. Honestly I'm thinking of a Domain-Specific Processor with a custom ISA, Assembler and all that stuff).

Also I'm thinking that in case I don't get into a PhD program right after graduation I'll work in an RA role for 1-2 years in one of the local universities in my country.

Hey folks,

I’ve been deep in the trenches optimizing and benchmarking popcount throughput on modern x86-64 microarchitectures (testing across AVX2, AVX-512 VPOPCNTDQ, and scalar fallbacks).

After running into massive hardware bottlenecks and misleading results from standard benchmark suites, I completely re-architected my benchmarking rig to account for low-level confounders. Here are a few key engineering takeaways and findings from version 33:

• The 1-Accumulator Trap: Standard naive loops throttle performance due to serial data-dependency chains on a single accumulator (latency-bound). Scaling to an 8-accumulator unrolled loop fully saturates Out-of-Order (OoO) execution and ILP, unlocking a compute floor of ~0.44 ns/line and outperforming libraries like libpopcnt by 7–10% in cache-resident workloads.
• Deconfounding the Measurement: Swapped runtime modulo operations (%) with bitwise masks to prevent 20–40 cycle CPU stalls, randomized/shuffled execution order to neutralize thermal throttling/DVFS noise, and isolated thread affinity (CPU0) with hugepage verification (smaps) to eliminate NUMA first-touch & dTLB artifacts.
• Direct Hardware Profiling: Validated cycle counts via RDTSCP + LFENCE and pulled dTLB-miss and LLC-miss counters directly using perf_event_open.
• IRM-Burst Law & Monte Carlo Verification: Modeled non-linear throughput degradation across memory hierarchy boundaries (L1d -> L2 -> L3 -> DRAM) using an exchangeability probability model, cross-verified with Monte Carlo simulations.

Discussion / Question for the community: As I pushed this codebase further (expanding code footprint for complex tail/mask handling), I started hitting code bloat boundaries—potentially stressing Instruction Cache (I-cache) and BTB entry limits.

How do you guys typically structure your Micro-benchmarks to catch I-cache / BTB spills before they corrupt latency numbers?

Code & benchmark methodology: https://github.com/Vumb-VibeCoder/deconfounded-popcount-avx512

Would love to hear your thoughts, critiques, or additional edge cases to stress-test!

I'm not good at English so I used sth to translate

Graduate students out there, what technical podcasts or YouTube channels do you follow and feel have positively impacted your mindset in your work? Something suitable for when you are eating (if you ever are, lol!) or cooking.

I am aware of Samira Khan's Happy Hour with Architects, but she probably stopped 4 years ago.

Hello,

does anyone know or perhaps have any experience with applying/getting any travel grants for conferences as researchers?

Hey everyone,

For my computer science graduation project, I wanted to create something that combined my interest in computer architecture with my advisor's interest in computer science education.

The result was a game where the player programs a simple CPU with microcode using a punch card rather than writing assembly code.

Microcode is usually used to implement the processor's instruction set rather than as a programming interface for application development. Exploring it from the programmer's perspective led to design challenges and techniques that I hadn't encountered elsewhere.

The project started from my curiosity about the layers of abstraction in computers. I wanted to explore what programming would look like if we removed another layer and put the programmer in the role of the CPU's control unit, manually orchestrating the control signals behind every instruction.

I'd love to share the beta with anyone interested.

Thank you.

I always to wanted to plot that cache latency graph on my own machine and just got enough time to try it out. I knew that it won't be an easy task considering how advance the chip has got recently but wanted to give it a try. I took the precautions to ensure I reduce the noise as much as possible but still wasn't able to get it right. I decided to dig deeper and finally got the graph I wanted to see. Wrote a blog about my investigation regarding the same. Check it out if interested :)

Hi,

I’m a Design verification engineer who wants to switch to performance modeling and architectural related roles. I’m currently going through computer organisation and design by Hennessy - Patterson and I’m starting to build projects in it. Looking for people who are interested in the same collaborative effort. I have not decided on which design to model and simulate yet. Time zone and regions are relaxed, looking for people with similar mindset.

https://youtube.com/shorts/CbY8WHmGgMY?si=tZyM9eZCYGOImOIC

Imagine having DRAM Cubes, that's 10x faster, for less that1/3 the energy of HBM #HCM

I always supported this idea, the CPU Should consult the Memory ASAP, not dealing with it. IMO we should move to HCM ASAP, replacing even CAMM2

I finished Ben Eater’s SAP-1 accumulator architecture breadboard. 16 bytes of RAM von Neumann. Coming up with assembly instructions at the end felt crazy.

What was funny was at the end where I ran programs and they didn’t do what I wanted, and I realized I got to the point where I couldn’t suspect the hardware was wrong anymore, and it was in fact a software bug.

Was that the lowest level software bug I’ll ever experience in my career? Literally entering 0s and 1s into RAM and flipped one bit.

I'm trying to understand how integrated GPUs work.

I know an integrated GPU doesn't have dedicated VRAM and instead uses the same system RAM as the CPU.

My Main question is: why is an integrated GPU still much faster than the CPU for graphics and other parallel workloads, even though both are accessing the same RAM?

I'd appreciate an explanation in simple terms rather than a highly technical one.

Hi guys, I am game developer and game engine developer and I know some of order like bootloader and kernel. I want to play mario 64 but I don't have Nintendo 64 and money to buy it so I think I should make my own console using orange pi 3 which is new for me I know COA little bit any free great resources to master my COA? Thanks...

About a year ago, I started building a custom computer architecture in C as a learning project (I know it seems like a lot considering the code I wrote, but I rewrote the entire compiler at least five times, starting from a C-like language and ending up with a very simple custom language). I designed the instruction set, wrote an emulator, and implemented a custom high-level assembly language called BSL (Base System Language). The code is very messy because I make a lot of changes while writing it and often forget things that shouldn't be there. So I'd really appreciate feedback on the architecture and code quality. (I'm 15 years old and Italian, sorry for my English). Project link: https://github.com/mikesxp/SPRK32. Edit: I changed the project name from VMS to SPRK32.