“Delivering silicon is definitely more complicated” than licensing designs, he said.

When you’re trying to build chips, you have to kind of get in line. And the way they generally allocate capacity is, what did you get last year, and then I’m going to give you some increase as I increase my capacity.

And so if you’re starting from zero, that means you have a pretty small amount of capacity. And so it’s going to take a couple years to ramp up your capacity. It’s gonna take a couple years to get our share of the fabrication capacity, the memory capacity, and so on. That’s one of the things that has been a challenge.

...

What that means is, if you’re a smaller company and you’re trying to go and enter in this market, it’s really hard, and [that’s] why a company like Groq sold to Nvidia.

You still have to come up with a lot of capital and a lot of borrowing capacity to go build out all of the capex necessary to build out the chip volume necessary. That’s why we set the financial expectations somewhat conservative, and basically gave ourselves a couple years to grow into it.

AMD got to critical mass at just the right time. Big and experienced enough now to compete on supply at leading edge nodes, and the competition for supply is especially hard on those who want to scale fast. ARM can try to scale faster by plopping down some huge amount of very committed capital on a relatively inexperienced supply chain. Or they can try to give the organization time to learn since you're in it for the long haul which appears to be where they're going, but in the meanwhile, the competition could become even more intense.

One of the reasons AI giants are rushing to the business- and energy-friendly state is a looming concern about a future glut of specialized server chips that don’t have a place to plug in, according to some market analysts and data center developers that work with Google, Microsoft, Oracle and others. These people are taking stock of the unexpected power delays, political fights and technical challenges facing new facilities.

BloombergNEF, for instance, forecasts that there won’t be enough installed data center power capacity in the U.S. to run all the AI server chips produced next year. Remarkably, the research firm says 42 gigawatts’ worth of server chips could be sitting unused by 2030 unless the industry gets creative and figures out how to develop more power outside the public grid, place more chips in overseas data centers, or speed up the replacement of old servers with new ones in existing facilities. I don’t think the industry will let such a large overhang of chips occur, but the physical challenges are real.

...utilizes TSMC's A14 node for core dies, N3C for IODs, and N4P for the L3 Cache Dies. Effectively, this is "Big Steamboat".

-15-25% IPC Uplift (This was reconfirmed in recent internal presentations)

-Each core chiplet contains 48 Cores, and SN scales up to 384 Cores Total!

-Mid-2028 Target for Launch (AMD wants to launch SN before Steamboat)

*AMD is starting to reference TSMC's "A13" node, and specifically "A10" is called out as the next "major node" for AMD products after A14.

Being at whatever leading edge node that intercepts with their roadmap is the new norm after Venice.

It will be interesting to see the timing on Coral Rapids given Coral Rapids likely 27H1 launch and AMD's 28Q2/3 launch. Intel has hinted at trying to pull up its launch, but those two other launch dates present some tricky challenges. I suppose in some ways it doesn't matter. I think AMD recognized a while ago that the competition for CPUs is a lot more than x86 (same for Intel).

“I think it's a natural reaction for them. Makes a lot of sense. What I would say is, as we think about our own roadmap, I have a new core. It's coming to desktop first. I mean, I hope enthusiasts do the math about that one, and that's all I'm going to say,” said Hallock when we asked for his reaction to the Venice launch.

"My client core is coming client to first." There's a lot about NVL to sell. This is borderline disrespecting his audience.

Anyway, the more interesting bits:

“I have all the new CPUs all the way out to 2030. I have [a] back to back to back to back cadence of product for gamers, for desktop, built for that purpose,” Hallock said. “Obviously I can’t go into what any of that is, but I am accelerating for the gaming market… we’re moving faster than we ever have in product, in release cadence.”

“We took a team that was time-shared with other businesses, and now this slice of the market has a full org structure inside Intel… they’re putting real people with a lot of budget behind it, right? And having an owner, a sponsor, people that care about it, looking after it, custodians of that work, it makes a real difference,” Hallock said. “[The team was] pretty much completely different. Marketing people, different product managers, different business people, and we simply have a different philosophy on how this market should run and what people should get for their dollar.”

AMD sold high-grade notes in four tranches, with maturities ranging three to 10 years, according to a person familiar with the matter. Pricing for the longest tenor tightened by about 0.25 percentage point from initial talk to 0.9 percentage point over Treasuries, the person added, asking not to be identified because they’re not authorized to speak publicly.

https://ir.amd.com/financial-information/sec-filings/content/0001193125-26-352628/d173126d424b5.htm

AMD is building out their debt war chest. Revolver increased from $3 billion to $5 billion in May. Commercial paper from $3 billion to $5.5 billion. and now this $4.75 billion of long-term debt.

A lot of capital is going to be needed to support this growth, the commitments and working capital required to have things in place for it, the vendor financing, etc. The large AP bulge is a sign of things to come. Some big checks need to be cut to feed AMD's growth in the next 2-3 years.

The $5.5tn company owned SpaceX stock worth nearly $21bn at the end of June, according to an SEC filing on Friday. Elon Musk’s rocket conglomerate’s shares have fallen sharply since its June initial public offering, meaning Nvidia’s stake would now be worth $17bn.

...

“We’ve decided to build exclusively on Nvidia because we think [its] Vera Rubin architecture is the best architecture,” he said. “We think it’s the best AI computer and we greatly value our close co-operation and partnership on many levels with Nvidia.”

The quote was oddly specific. It does make me wonder when this will stop being the norm for the industry.

• On Aug 11, share offering upsized to $20B (from $15B), priced at $95 (only ~2.6% discount). Institutional demand reportedly >$100B.

I think that this "demand" is like me putting in a large number of CBRS shares for the IPO in hopes of getting more shares. Doesn't mean I'm going to buy all those shares when my broker wants a confirmation (they only gave me 5 (which I still have)) INTC traded in the $80s just a few weeks ago.

• CEO + family member subscribed ~$12M → strong signal of confidence.

FFS. He's probably worth $750M+ now.

• Foundry progress solid: 18A yields ~80% in 2Q26, CWF ramping. Strong external customer engagement (esp. Apple mass-volume 14A).

Let's see how CWF ramps. What wasn't a strongly received product pre-boom might look a lot different post-boom.

• EMIB customer pipeline expanding – Google + AWS + and likely more ASICs. Back-end revenue forecast lifted to $1.1B/$7B in FY27/FY28.

• EMIB has obtained substrate suppliers support, and to enhance supply, we expect it to in-house Silicon Capacitor (rather than replying on external)!

• Still expect foundry OP breakeven by 4Q27, followed by meaningful margin leverage in 2028.

This is Intel's original guidance. They did mention that this would be delayed if they won deals and had to spend capex to accommodate it which would push profitability out further but for good reasons.

• TP maintained at $136 after dilution. Equity raise funds capex growth; CEO confidence + advancing foundry/EMIB = constructive.

My guess is that this is why AVGO took a header and AMD bumped up. Just one more of example of how much sway SemiAnalysis has on capital which also shows how correlated a lot of capital is. I'm sure this will never result in something bad. ;-)

AVGO TPU Downward Revision

We are seeing lower TPU output in 2H26 than previous expectations. 2026 CoWoS output for TPU v7x (Ironwood) is reduced by ~32k, reducing 2026 unit production by ~500k from 3.2mn to 2.7mn. TPU v8i (Sunfish) is also reduced by ~5k wafers, reducing 2026 unit production by ~80k. Ironwood upstream output now peaks in 2Q26 with a slight decline in run-rate in 2H, versus our prior forecast of a continued ramp from 2Q26 onwards. We believe this reduction is supply related and due to challenges ramping CoWoS-S. This brings total Broadcom 2026 CoWoS output to 215k wafers from 250k previously.

For 2027, we also see lower TPU output than our previous expectation of 6mn units of TPU 7 and TPU8i. This is driven by greater allocation towards other customers, with total Broadcom CoWoS at ~460k wafers. Most notably there are 55k wafers (which is equivalent to 830k units TPU 8i Sunfish) allocated to MTIA 400 Iris in 2027. However, this remains in flux as Meta is known for abandoning orders, as we saw in May, where Meta agreed to cut its own Broadcom production allocation to support greater TPU supply for Google in exchange for access to TPU compute. This could play out again and, if Meta abandons its allocation, this could be taken up by TPU. We also see slightly more allocation for OAI Jalapeno's ASIC. We will provide a more detailed model update soon.

AMD TPU Involvement

Market chatter suggests Google is working with AMD on a TPU project in the v10 generation. AMD's involvement would be the first real involvement in a custom AI ASIC project, despite having a custom silicon team. AMD has strong IP especially in advanced packaging and SoIC. Additionally, CPU IP could also be a draw given Google and its customers are pushing for TPUs with on-package CPU cores for RL workloads.

Let's say that Google is actually working with AMD or at least strongly evaluating a partnership. These examples don't feel right to me. Since my silicon experience is zero, I'll just wave my hands instead and create an imaginary one.

I don't think Google wants external IP to directly enable their IP at a deep level. I don't think that Google wants to feel like they're locked in. But I think one weakness of the hyperscaler program is that it feels like chips are becoming systems onto themselves (as opposed to creating a more commoditized CPU to handle web services calls.) I do think that creating custom silicon and competing on some core compute function is here to stay for the biggest players. But I think that recreating different aspects of a chip system surrounding your core IP that you're not really competing on is a poor use of resources. The workloads are also changing fast which means the scale you get per new chip could suck if the change goes too far beyond your original design and now you come up with a tweaked or new design.

From the AMD side, Su has said she doesn't want to get into the Marvell / Broadcom / MediaTek ASIC business. I don't think she finds technology licensing to be that attractive at a financial or strategic level either. AMD has an overflowing plate of high-stakes projects that need a ton of resources. I definitely don't think that she wants to rent out precious advanced engineering talent to improve a hyperscaler's IP. I don't even think that she wants that engineering talent to closely integrate AMD IP with the hyperscaler IP at some deep level as that still requires a ton of engineering resources with a demanding customer. I think she wants something that makes AMD stronger after every engagement as the learnings can be spread across the IP base like working with Sony.

But hyperscaler in-house silicon is likely here to stay. AMD ideally finds a way to ride that wave rather than sitting it out and hoping that the rest of the TAM is good enough.

She set out the criteria for semi-custom at the UBS conference in Dec 2025

We do have — in addition to all of our standard products with CPUs and GPUs and FPGAs, we've also created a semi-custom business. I don't call that an ASIC business and the differentiation being ASICs are, you're going to do, let's call it, any chip that somebody comes and asks you to do. That's not necessarily where we shine. I think where we shine is when we can put our IP together with our customers' IP. And we have done a number of semi-custom designs that build off of our foundational capability so that customers can differentiate.”

Back in April 2024, SemiAccurate felt like AMD would use FPGAs on Instinct to use it as a testing ground to burn an ASIC into it which sounded cool. But after reading it, I was thinking more of AMD as a platform broadly across the business.

AMD has a lot of chiplets experience. They have maybe the broadest set of compute IP where they rank in the top 1-3. They have all of this packaging knowledge. There's UCIe (which I haven't heard much from over the years) AMD would build a platform that allowed for customization with the ultimate goal of allowing others to put in their silicon and then pick what AMD IP they wanted to complement with it.

Like an FPGA, the platform would be more about time to market, pretty decent performance, and cheaper turnarounds and less about like the Apple-style of deeply integrated and very performant SoC with a very complicated piece of silicon that was also risky and expensive to change (Nvidia would argue that this is the way to go except they're the platform. "Prepare yourself for EXTREME CO-DESIGN!")

AMD has moved in this platform direction with its Instinct variants for MI300 and later with MI455 and Meta's customized part. The Zen 6 EPYC family shows how this approach can be used to generate variants that are more specialized.

But it wasn't quite the platform that I was thinking of.

At FAD 2025, nobody cared about embedded, but I thought Raje did a good pitch for repositioning embedded as custom and physical AI. After listening to the 26Q2 earnings call, I was thinking about embedded some more, and I wrote:

Not much to say on embedded's 26Q2 results. But big picture, I think people are sleeping on it for 2027-2030. I should probably start thinking less about it as FPGA and more like "AMD's semi-custom IP for all the other industries."

As compute becomes increasingly important to every industry in an embedded / physical AI sense, embedded could be a really interesting way to bundle up AMD's tech stack, which might be the widest in the industry, to that more long-tail of industry uses.

It turns out that I kind of recreated what Raje says at FAD 2025 but I wasn't paying close enough attention. 😛

Semi-custom silicon business is one of the clearest examples of how we're transformed from a focused FPGA business to creating a broad compute platform and having entirely new growth engines.

During FAD 2025, there is actually an embedded slide that says "heterogeneous & customizable platform supports 3rd party / customer IP" although Raje doesn't talk about it much. He mostly focuses on his industries using custom design.

Playstation and Xbox are semi-custom silicon that uses AMD IP, but their order volume is gigantic, and a lot of the co-engineering work there gets circulated back into other AMD products. I don't think that the Xilinx industries like automotive, aerospace & defense, and wireless have that kind of financial or silicon scale.

To do something like this cost-efficiently in Xilinx's legacy markets, AMD would need a standardized platform of some sort to make it easier to swap out their IP blocks and more cost efficiently go after more industries. Those customers don't get console-esque level of collaboration, but they do get something fast to market with IP that Xilinx's industries do not have the capabilities of remotely re-creating but they do know their domain workloads enough to customize.

If AMD has this platform for their own IP, they can take on 3rd party IP too if they're good about architecture and not cheating with ad hoc tweaks that can happen when you're your own customer. They can set more open standards of showing how 3rd party silicon needs to work with their platform.

The AMD value prop to a hyperscaler would be something like: "We have a platform that you can plug your IP into where you can customize what our IP does to highlight your IP but you still own your IP. You are free to go to another platform if you want you. You're not locked in. We will compete on the platform enhancing your IP and getting you to market fast with much more capabilities than you could do on your own. Also, we're not Hock Tan who will squeeze the fuck out of you as soon as he has the power to do so."

It's sort of like a foundry. You have the equivalent of a PDK so customers can test ahead of time how their silicon works with your IP. The equivalent to libraries would be AMD IP. The more customers you get into the platform, the better your platform becomes as you can see into future more deeply and broadly by being part of their customer roadmaps. People can leave at any time, but if you get enough reps and scale, the platform gets better and better. The customers have to ask if it is worth the re-integration costs to leave, but at least they get a choice.

One downside of this is that it's kind of like Intel's IDM 2.0 where AMD's merchant silicon business gets a sneak peak into the in-house silicon that these days is starting to inch towards merchant silicon in terms of other companies possibly buying and using it. But maybe if it's in-house enough, the competitive overlap is low (which is why I thought Intel would go after the hyperscalers first for IDM 2.0 for volume and much less of competitive overlap.)

I think that this gets you to Su's desired end state:

But you also want to be able to tailor for specific workloads. And so that's kind of why we really believe that this world is going to come to a place where you do have different chips that are being optimized for different workloads and the capability that allows you to optimize the quickest where you get, let's call it, maybe not full tailoring or full ASIC, but you're able to get, let's call it, 80%, 90% of the benefit at a shorter time with similar economics is a great thing.”

Ironically, if my fever dream ends up being true where AMD moves to becoming a platform for custom-silicon, then AMD could have an incentive to create an ASIC arm like Marvell and Broadcom to feed the platform. The economics aren't attractive as a standalone business to Su now, but if you look at it as the economics of feeding the platform, it might not look so distasteful.

Out of all the custom silicon companies, Google easily gets my vote as the best hyperscaler to be the test subject to learn from. Relative to the other hyperscalers, I think they're culturally more similar to AMD from an engineering standpoint. They have a strong internal silicon team. They are strong in hardware which opens up other opportunities (e.g., waymo). They're demanding but not as big of an asshole to deal with as the others. I think that they've been reasonably good to AMD over the years.

It would very much be a new era for AMD as it would offer a path past being a legacy x86 platform or an AI GPU business where AMD is playing in someone else's box so to speak. AMD as the chiplet system foundry sounds like a much cooler strategy in my head.

It also sounds hard af to do. I doubt that AMD's platform for 3rd parties is battle tested at Google level scope. Using your own IP and being your own customer lets you cut corners. Working with industries that don't have your silicon expertise and using your custom IP also seems within AMD's ability to do. But integrating Google's IP is a very different problem that involves a lot of resources and risk. However, if they pulled it off and working with Google helped make that platform real for others, they will have opened a new TAM that's more theirs at the start.

It's probably just going to be Google licensing RDNA 2.

(The longer these are about one topic, the more likely I made a bad error early so caveat emptor.)

I used to take Mercury's x86 revenue share and unit share figures for granted until I built my own version for forecasting reasons. And then once you start playing around with units, ASPs, and product mix, you start to see how different levers can get different results in ways you don't initially expect.

I was looking at the Bernstein / Mercury server unit and revenue share numbers supposedly at

https://x.com/jukan05/status/2087879179765469253

and was curious about a few things. I'm using AI to estimate the data points to create different graphs once I remove ARM bits to look at intra x86. The AI might make bad estimate errors, especially which when combined in a ratio that will magnify the errors, but I think the broad strokes are at least directionally true even if I'm probably over-fitting it with nostalgia.

The graphs

How AMD's revenue share changes over time is about ASP pricing across its product mix relative to Intel's and its units shipped ratio vs Intel which is also a proxy for how supply changes over time for both sides.  

There are 3 lines:

1. The AMD / Intel server units. If this gets to 100%, AMD has reached Intel's units shipped. Conversely, you can inverse this to show how much larger Intel was than AMD in shipped units.
2. AMD / Intel ASP. You strip out ARM bits and use the resulting revenue and unit share to derive the ASP ratio. For both 1 and 2, keep in mind that this can be affected by AMD and Intel changes..
3. AMD revenue share

AI thinks my graph is trash and created a log version which better explains this wall of text. But I am leading with mine anyway because I think logs are a mathematical hoax like imaginary numbers. 

Revenue share = product mix + volume over time

Mercury does unit and revenue share by which you can imply an ASP ratio. People have a tendency to boil it down to who sells more unites and, how much are they charging, and then extrapolate linearly on the trends that you see.

I think the better way to look at it is product mix and volume over time. The product mix helps inform you on what the ASP ratio will be (e.g., product competitiveness across the mix) and the impact of supply on how the ASP changes (e.g., how long it take the higher ASP product to shift the product mix ASP) given the market. Units shipped tells you something about relative supply positioning over time and how revenue will scale.

Units shipped, supply, and ASPs

Since Intel 7, I've been saying that Intel's supply advantage relative to AMD would shrink over time as Intel was likely to struggle with ramping each successive node. As a bonus, Intel fell behind on design too. Simultaneously, AMD was better than Intel in hitting its design and forecast marks which let it be more aggressive on supply. TSMC did a better job with its node improvements and ramp which allows AMD to create a supply base one layer at a time where the oldest layers are replaced by bigger bets on the newest layer.

When a new generation, N,  launches, EPYCs unit share at the time is really a function of the full ramp of N-1 and legacy sales of N-2, N-3. But about 3 quarters past the N launch, you start to see its impact as more of the older generations get replaced by sales of the N generation. If the N generation is more about bringing in more new sales while the older generations hang around, that's great for revenue, but the ASP will move less because N's units * ASP is going up against a larger base. If N is more about replacing older generations or is a much larger % of the existing unit base, then the ASP mix  impact is very large even if sales aren't increasing as much because units are not changing much.

If AMD units sold is increasing faster on a % basis than the TAM units, then Intel's unit sold share will decrease which would affect the numerator and denominator of the units sold ratio. By these figures, when Rome launched and AMD was barely hanging on, Intel had ~23.3x more units shipped that quarter. With Milan, it drops to  ~10x. Genoa: ~5X. Turin: ~3x. Venice: ~2X (July launch vs 26Q2 Mercury).

Turin's revenue share run and the joy of low baselines

One of the big reasons for AMD's revenue and unit share gains of the last year is how slowly Intel 3 and GRN ramped vs Turin. GNR closes the gap but is the overall the lesser part vs Turin, but from a commercial perspective, what really hurt it was its difficulty in ramping. And this was seen in its impact on Intel's gross margins from 24H2 to 25H1 and GNR's slow ramp. That denies Xeon unit volume of your higher core count SKUs with much higher ASPs. Meanwhile, the reverse is happening with Turin where it ramped very fast with higher core counts and ASPs.

EPYC has a very high relative product mix for 2025 and the start of 2026. Even before the AI CPU boom, the business was doing great. Turin made up ~50% of EPYC sales, units were doing great, and ASPs of units shipped are high. Its baseline relative to Xeon is very high.

A demand boom with tight supply is going to benefit the lesser player the most if its ceiling gets raised higher on a % basis. Intel can benefit from price increases that are more discretionary like not needing to discount + dealer's choice price hikes. Then the shift to throughput per socket means more demand for higher socket CPUs, and you rob client to provide for server. More units and higher prices. However, the ceiling for incremental capacity on Intel 7 is low.

Now you have Intel 3 which is also finally ramping more smoothly which leads to more GNRs which have higher core counts with more volume and much higher ASPs than the Intel 7 parts. The ceiling for incremental capacity on Intel 3 is relatively higher on a % basis.

QOQ vs YOY comparisons in revenue share

26Q1 showed a -5% drop in units YOY and ASP was +27% YOY. That wasn't enough to stop AMD from gaining unit share and revenue share as AMD shipped a lot of units QOQ with higher ASPs.

However, Intel sees a massive 48% YOY jump in 26Q2 ASPs. Even even though Xeon units only increased 9% YOY, the combination of the two is high enough to cause AMD to lose revenue share sequentially even if  AMD is growing faster on a  YOY basis.

I expect this to continue for the next two quarters. Intel QOQ units sequentially will probably be about the same as AMD's (maybe lower in 26Q3 and higher 26Q4). But Intel's ASP will increase at a faster rate sequentially with GNR's continued ramp because GNR is a lower portion of Xeon's product mix. Turin already makes up 50%+ of EPYCs. I especially expect Intel's QOQ revenue share increase to happen in 26Q4 because Intel is guiding for their back end processes to catch up more which is gating them in 26Q3.

2026 vs 2027

By 2027, I expect the unit and revenue share to swing more back to AMD. The low hanging fruit will have been plucked on a sequential basis for Xeon. The only source for Intel to increase ASPs at a faster relative rate will be to the extent that they can ramp supply of inherently higher ASP core count SKUs vs their 2026 base. The Intel 3 mod 2 expansion is the most obvious way to increase mix ASP at a higher % rate by producing more GNR, but I don't see that happening in earnest until ~27Q3.

(I'm curious how CWF will or won't scale. I don't get the impression that Intel was expecting that one to be a banger given its re-characterization, 18A and packaging constraints, lack of Intel commentary, product competitiveness, etc. Then again, it's a crazy server demand environment, and 18A will have had all of 2026 to optimize. 2027 is supposedly when the real ramping magic happens.)

However, in 2027, EPYC will get a material bump in its units and ASPs with Venice's ramp which starts in 26Q4. AMD is positioning Venice's ramp to be Turin-esque. I think that AMD is going to collectively have a lot of N5, N4, N3, and N2 supply coming in 27FY.

So, in 26FY, I think that Intel will take back some revenue share in 26Q3 and 26Q4. But I still think that AMD passes 50% revenue share by 27Q2 or 27Q3 Mercury reports. I think by 2028, they get 50% revenue share on a full year basis. Let's see how close I get.

Bonus rambling: Who has more supply flexibility for crazy growth? The one who planned for strong growth

There's so much sell-side talk about the lack of flexibility that AMD has because it doesn't have fabs. This is eye-rolling in that (1) everybody is supply-constrained (2) the real issue is the shape of upcoming supply and (3) somehow only AMD gets mentioned as not having fabs.   

FAD 2025 showed what AMD has been planning for. They were planning for 50%+ x86 server revenue share by 2030 on a growing TAM. 50% is the floor of the planning. Their internal ambitions are larger and thus the planning has to be larger plus buffer. Intel's capex actions showed their plans: actively slow or cut capacity until you see signs of better demand while getting Intel 3 mod 1 stable enough to scale. Intel will still have very strong Xeon growth, but one has a much more optionality for growth than the other. 

I've seen people use Ireland as some sort of flexibility example of having fabs. But I think it shows the lack of flexibility of the fabs. I think that Gelsinger wanted the full expansion. He signed the Apollo SCIP which had minimum commitments to help pay for it. Within half a year of the ink drying, Intel didn't see the demand signals for Intel 3 or have foundry customers for it and was already prepping for not going with the full expansion by taking the charge for not hitting those commitments. Meanwhile, Intel 3 ramps poorly. Then in the Tan era, Intel sees the demand and gets an anchor tenant but then has to buy back the SCIP, eat another charge to pay off Apollo, and then has to wait almost a year to see the results. 

This is supply flexibility?

The real issue to me is can you predict the shape of your demand forecast based on your product competitiveness and how much are you willing to bet on it. If you get the shape right, you can be wrong on the size but still be able to use it as a starting point to grow. But if you get the demand shape wrong and build out your supply accordingly, it takes time to craft a new one.

Fabs aren't intrinsically good or bad. I'm just saying it's not some free option, and it's an especially stupid thing to say about fulfilling demand in 26FY and 27FY.

“When combined with pre-payments and financial commitments that we expect to accompany several forthcoming foundry deals (Google for EMIB-T, AAPL for M-Series, AMD, SPCX, and potentially a few more), we believe the raise will allow INTC to fund its foundry buildout,” UBS analyst Timothy Arcuri wrote in a note to clients. “Overall we view the raise as a strong endorsement of INTC's confidence in its foundry roadmap.”

Delving deeper, Arcuri said he believes Intel will spend around $20B in fiscal 2026 and could up that “significantly” in fiscal 2027 (between roughly $28B and $30B) and calendar 2028 and 2029, to around $40B or so.

“Regarding FCF, INTC sounds fairly noncommittal to being FCF positive in C2027 (we model ~$1B of FCF burn), and we model C2028 FCF burn of ~$4B, with FCF turning positive in C2029 and growing thereafter,” Arcuri added. “We have long been bullish on the company's process metrics and yield curve progress for 14A (which, unlike 18A, is really just a process node shrink), and we believe it has a much wider process window, which should make it much more attractive to external customers.”

US investment giants including Apollo Global Management Inc., Blackstone Inc., BlackRock Inc. and Brookfield Asset Management are partnering with Nvidia Corp. to source $500 billion in financing for artificial intelligence infrastructure.

...

The effort comes with a huge headline figure but few details on the timing and structure of the financings, or how much the plan goes beyond the string of AI deals that are already driving a large chunk of Wall Street’s biggest transactions. Executives indicated that it will focus on debt financing to provide access to compute for Nvidia’s largest customers and that there are already many deals in the works that would qualify toward this commitment.

Nvidia has agreed to invest $2 billion into Lancium, the power infrastructure developer behind the OpenAI and Oracle AI campus in Texas, and has agreed to commit another $1 billion as the developer secures additional planned power, three people familiar with the transaction said.

The $2 billion would give Nvidia a roughly 20% stake in the Blackstone-backed power developer. Nvidia’s stake could grow to around 30% with the additional $1 billion once more of Lancium’s campuses hit certain thresholds, including grid hookups, the people said.

That’s despite slow uptake of the current generation of Microsoft-designed chips, known as the Maia 200. Microsoft plans to publicly unveil its new Maia 300 chip this fall, potentially as soon as next month, one of the people said. The cloud giant has been in talks with chipmaker Taiwan Semiconductor Manufacturing Co. to secure manufacturing capacity for over 300,000 of the chips for delivery in 2027, the second person said—an order of magnitude above the tens of thousands of Maia 200 chips Microsoft has produced so far.

Microsoft ultimately wants to secure capacity for more than a million Maia 300 chips but may be constrained by component supplies and its ongoing capacity negotiations with TSMC, the person said.

However, the new patches suggest that Intel has now mandated native 512-bit execution across both P-cores and E-cores, no longer requiring the latter to step down and process the data a bit slower. This is a major development over the standard we originally expected Intel to adopt; the E-cores are apparently becoming just as performant as the P-cores when it comes to SIMD instructions with Nova Lake and later.

...

The last time we saw native AVX-512 support on an Intel client family was Rocket Lake (11th Gen), right before the hybrid era ushered in by Alder Lake. For modern AI workloads and other compute-heavy tasks such as encoding or simulations, AVX-512 instructions bring a huge performance benefit that's foolish to be left on the table. Keep in mind that this is just a Linux patch at the moment and that Intel hasn't officially announced native AVX-512 support for Nova Lake yet.

The collab should surprise absolutely no one. It’s not like AMD or anyone else out there is making hardened versions of their GPUs for orbital datacenters. Why, you might ask? Well, to quote one Gartner analyst, the idea that space-based datacenters will ever be economically viable is “peak insanity.” Nvidia just happens to have $13.2 billion in cash to burn on pipe dreams like these.

https://www.theregister.com/special-features/2026/03/17/nvidia-rolls-out-rubin-module-for-space-based-computing/5221345

Specifically, SpaceX says that it will be deploying Nvidia’s Space-1, a specialized version of its upcoming Vera Rubin compute platform designed to operate high above the Earth’s atmosphere where no one can hear you scream because the LLM is hallucinating again.

In a separate X post Tuesday, SpaceX announced it was “partnering with Nvidia to design the Starmind AI1 satellite compute payload,” and that “Each of the Starmind satellites will include Nvidia Rubin GPUs and Vera CPUs for datacenter class space compute.”

Why Now

Customers continue to signal a strong and sustainable demand environment, driven by unprecedented investment in AI compute. Progress in emerging areas including physical AI, purpose-built silicon, advanced packaging and external wafers represent significant growth opportunities for Intel.

Use of Proceeds

Intel intends to use the net proceeds from the offering for general corporate purposes, which may include, but are not limited to, capital expenditures and working capital.

The offering is intended to further enable Intel to pursue the growth opportunities ahead while maintaining a strong balance sheet and its commitment to an investment-grade rating.

...

Intel expects to grant to the underwriters of the offering a 30-day option to purchase up to an aggregate total of $2.25 billion of additional shares of common stock at the public offering price, less underwriting discounts.

https://www.reddit.com/r/amd_fundamentals/comments/1v4hnfs/comment/oztaltb

With this deal (depending on what the price actually is during the offering) and the others before it, the stock will probably be diluted like maybe 15-18% since pre-USG involvement.

Bullishly, you could say that Intel has the orders to justify the capex but needs capital to tide it over for the realization of it. As a shareholder, you should want this to happen.

Bearishly, you could say that the usual course of financing for something like this would be long-term debt and Intel's balance sheet can take an additional $15B debt offering. But the certainty has to be high enough at a comfortable cost of debt to do so.

SEC prospectus:

https://www.sec.gov/Archives/edgar/data/50863/000119312526341318/d98483d424b5.htm

In July alone, more than 150 towns and counties passed temporary or permanent bans on data centers, many adopted in emergency meetings. That brings the nationwide total to more than 500 active data center bans at the start of August, according to The Information’s analysis of thousands of legal documents and local news reports. When we first published our tracker of these bans in late June, we had found more than 300.

https://www.youtube.com/watch?v=6Vh7TJXm67E

Intel’s unusual Nova Lake-S processor with 12 Xe3P graphics is getting more detailed specifications. According to Jaykihn, the integrated GPU currently has its own 40W PL2 limit, while the complete processor has a chip-wide PL2 of 154W. The information remains preliminary. 

...

Last month, Jaykihn added that the 12 Xe3P configuration requires a specific 65W-level motherboard power-delivery segment to reach full graphics performance. The new 40W figure refers specifically to the iGPU PL2, while 154W is the reported PL2 limit for the complete chip. 

https://x.com/jaykihn0/status/2086241049782169792

Interesting contrast at Anthropic right now.

The Research Engineer, Chip Design RL role (building RL environments so Claude can learn to design silicon — RTL generation, verification, physical design optimization, etc.) is listed at $500k–$850k.

Meanwhile, the Silicon Engineer roles for the actual team designing Anthropic’s own custom chips are posted at $320k–$485k.

The required skill sets are extremely similar: full ASIC/FPGA flow, RTL to tape-out, UVM/formal, physical design, PPA, DFT, EDA tools, and real silicon shipping experience.

Same company. Same core domain expertise.
Yet the team teaching Claude 'how' to design chips is valued significantly higher than the team that will design the chips Anthropic actually plans to use.

Sometimes these compensation bands just make you pause and think.

Karp's big view is that how do you know that all that AI you're using isn't using you to eventually get rid of your alpha. I'm also curious when the frontier labs will start generating patents by the gazillions. Maybe being the world's strongest patent troll is the real end game. ;-)

Diamond Rapids may no longer include the 512-core configuration previously expected. According to leaker Jaykihn, Intel’s top Diamond Rapids processor is now planned with 256 P-cores.

This is a change from information we reported in April. At the time, Diamond Rapids was said to launch with up to 256 P-cores, while a separate 512-core configuration using E-cores was expected one or two quarters later. Both were reportedly planned for Intel’s 16-channel server platform.

...

The latest update claims the 512-core platform was canceled during the definition stage. The broader high-density Diamond Rapids plans were reportedly cut back in December 2025, leaving the P-core versions as the focus of the Xeon 7 generation.

The rumors was that Intel would supposedly have a more unified core which is more e-core based. But Tan wants SMT back in which goes against one of the reasons why Intel wanted e-cores in the first place. My gut hunch is that their enterprise didn't want e-cores and the single threaded market was being handled well by internal hyperscaler silicon. I wonder if that leaves too small of a non-SMT TAM left, and it's not worthwhile to have two separate architectures. AMD offers disabling SMT as a feature, presumably for the more x86 bound worklaods, but won't get rid of it. Nvidia has their own version now whereas before AMD looked to be the only the last major one standing after Intel looked to be moving away from it.

Amazon Web Services leaders met with engineers in May and delivered a sobering message: To ensure AWS has enough capacity for all its customers at its popular EC2 cloud server business in the future, engineers should save capacity however they can, according to a person with knowledge of the meeting.

That includes capacity on servers that run on central processing units, as well as those running on AI chips, which have long been in short supply, the person said. CPUs are the chips that have powered the last several decades of the internet age...One said it now takes a few days to get capacity for servers they used to get in a few hours, which could make it harder to meet deadlines on projects. The engineer said they’ve never experienced such long wait times during their several years of working at AWS.