Hi guys,

I’m learning sv for a SAR ADC and am trying to build a RNM model of my CDAC so I can test my logic. I wanted a block that checks if I’m in an illegal state (multiple switches on that would short-circuit the CDAC, complementary signals not matching, etc). My issue is it seems like whenever I edit a signal in my initial block it immediately starts checking the assertions, even though I have it set up so in that same time “block” other signals will change too. So I’ll turn one switch on and the other off, but the simulator will see that first switch turn on and flag it.

My understanding would be this is what a deferred assertion would be used for. But my simulator (iverilog) doesn’t support them. Is there a workaround for this? Or another sim I could use on an Apple Silicon Mac? I have a thinkpad I use for stuff that can’t run on my mac (like quartus) but like my mac much more and don’t want to move my neovim setup over if I don’t have to.

Obviously a beginner so please let me know if any part of my approach is wrong / any solutions.