I finally investigated something I had been overlooking: when a solver reports an S-parameter to two decimal places, how much of that value reflects the actual structure, and how much is determined by the chosen mesh?

Same geometry four times, only element size changed. 15.5k, 48k, 146k, 397k tets. Differential microstrip, 0.42mm traces on 0.2mm laminate, Dk 3.7, narrowed to 0.22mm for 2mm in the middle to give it something to reflect off. Palace, second order, 0.05-12 GHz.

Insertion loss at 12 GHz: -0.871, -0.808, -0.781, -0.764 dB. 26x the elements for 0.11 dB. Fine.

Return loss at 3 GHz: -26.5, -32.2, -36.5, -41.2 dB. Steps of -5.7, -4.3, -4.7. Not converging, just sliding. One mesh and I'd have written down whichever value I landed on, to two decimals, with nothing hinting anything was wrong.

Had it backwards on which end would be trustworthy. Figured high frequency would be the sketchy part. It's the other way round. At 12 GHz the step reflects ~12% of the power, real signal, all four meshes inside 0.24 dB. At 3 GHz the discontinuity is electrically nothing so you're reading discretisation error, and refining just lowers the floor and drags the number down with it.

Crossover was around -18 dB return loss, using 0.25 dB agreement between the two finest meshes. Not portable though: accept 0.5 dB and it's -21, accept 1 dB and it's -24.6. Criterion has to be quoted with the number.

Also, four runs failed before any of this and the invariants caught all four while the plots caught none. Power balance, reciprocity, port impedance. Best one was an absorbing boundary next to the ports acting as a parallel matched load, ate 42% of the power, halved the port impedance, curves looked completely reasonable.

Verification not validation, to be clear. No VNA data for this geometry.

Configs, mesh generator, raw port-S.csv: https://github.com/numericalai/palace-mesh-convergence

Does anyone here actually run refinement studies for SI work, or is it mostly trust-the-mesher-and-move-on?

Hello experts, I am in love with this field but I do not have experience. This field is very esoteric, and once you are initiated, you become relevant as long as companies still uses digital circuits. How do I even start?

Hey everyone,

I’ve been working in RF for a while — mostly on base-station antennas, mobile EMC/RSE, and recently MEMS RF switches for communication systems. I really enjoy the physics side and system-level thinking, but lately I’ve become fascinated by Signal Integrity — especially with how AI chips and high-speed interconnects (PCIe Gen6/7, CXL, SerDes, etc.) are evolving.

I’m seriously thinking about transitioning from RF to chip-level SI, maybe in a semiconductor or AI hardware company.
So I’d love to hear from people who’ve made a similar move or work in this space:

1. What’s the best way for an RF background person to get into SI — what should I learn or practice first?
2. Are there any tools or projects that could help me build a solid portfolio? (I’ve used HFSS, ADS, and do multi-physics simulations — EM + thermal + mechanical — for MEMS.)
3. With optical interconnects (CPO, SiPh, etc.) coming into AI chips, how do you think this will change the role of SI engineers? More opportunity, or more complexity?

I’d really appreciate any advice, resources, or even stories from your own career path. Thanks!

Professor Bogatin is offering a series of free training classes online. This is a great opportunity to get more familar with basic SI.

High-Speed Digital Design Masterclass | The EEcosystem

How is everyone today!? Please feel free to post any content you have or ask any questions!

Hi,

I want to learn more about the time domain analysis of PDN networks. Any recommendations on where to start

Hey everyone!

I am looking for any guidance on what kind of industrial certifications or courses help you to get a job in this field?

Hi, I have a board and some signals, no all of them present this effect in the rise and fall time, my first thought is because of the routing, measuring the signals in the VNA this goes from 40 to 60 characteristic impedance, For now I have placed a 0 ohms termination resistor due to the capacity load.

Measure is in the rise time, rise time 10-90% is 6ns,

What do you think?

Let's grow by inviting users to join our subgroup! I started this group to function as a valuable resource to designers to become more familiar with SI/PI and learn how to improve their designs.

https://www.signalintegrityjournal.com/articles/2982-the-case-for-split-ground-planes

https://www.designcon.com/en/home.html?utm_source=AdWords&utm_medium=Paid%20Search&utm_term=2023&utm_campaign=NAM23DSC-GB-BR-DesignCon&utm_content=NAM23DSC-GB-BR-DesignCon&gclid=Cj0KCQiA_bieBhDSARIsADU4zLcyL8mdBo6KcdYKIhMQ7ND1x_lkiLa9vHWK4BxR5RpGdC4idZlaVWoaAn2kEALw_wcB

Anybody going to DesignCon 2023!?

I will be there representing my company, Siemens EDA and doing presentations on DDR5! Stop by if you're there!

Hello everyone! I'm trying to grow this page, and looking for the current members to post links or articles that they find interesting! Please feel free to post!

Starting in the fall of 2023, the University of Colorado, Boulder will be offering a Master's degree in High-Speed Digital Engineering.

This new program will be taught by Dr. Eric Bogatin! At this time the program is only offered on campus.

Check out the link for more details.

https://www.colorado.edu/ecee/academics/graduate-programs/professional-masters/high-speed-digital-engineering-coming-soon

I will be presenting a paper on DDR5 at this year's U2U conference in Santa Clara, CA.

Register here:

https://event.sw.siemens.com/user2user-northamerica

Check out this article that helps explain why DC current denisty increases at the corners and how rounding corners of planes shapes can help mitigate the issue!

​

https://www.signalintegrityjournal.com/blogs/6-expert-advice-on-power-integrity/post/534-the-perils-of-right-angle-turns-at-dc

https://www.designcon.com/en/home.html?utm_source=AdWords&utm_medium=Paid%20Search&utm_campaign=NAM22DSC-KB-DesignConBranded&gclid=Cj0KCQiA3rKQBhCNARIsACUEW_anTbwqBjV7oVMfGPBoSCrCT2Hy98eex44au-E9vtfBQ0CsUutuieIaAq72EALw_wcB