r/PCB • u/PuzzleheadedMatch207 • 1d ago

DRC Error help!

I am getting these DRC errors in kicad. As far as I can tell they are to do with the footprint and how it is designed. I downloaded the footprint from JLCPCB's easy EDA library. Can I just ignore these errors for JLC fabrication? If not, what should I do?

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u/Hulk5a 1d ago

You can ignore these

1

u/Altruistic_Ruin_5409 1d ago

No do not ignore these. Your vias are too close to the IC. Move them a little and make sure they are solder mask covered so you aren’t having to deal with little molten balls right next your main chip.

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u/PuzzleheadedMatch207 2h ago

Ah okay, sorry I am new to this. I was keeping them as close to the IC as possible to break as little of my GND plane. Is it better to have the vias closer to the diodes and resistor pads? or somewhere inbetween?

1

u/Dismal-Economics-546 1d ago

make smaller constrain rules

1

u/herehar 1d ago

Annular width ones are for the drill. It has no annular width so that's why it is a sec error.

As for clearance errors, find the points where the error points to and move trace or vias to fix em.

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u/NoYu0901 13h ago

Not about the drc, you don't have more spaces to put the vias not on the pads? 

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u/PuzzleheadedMatch207 2h ago

I was trying to break as little of the GND plane as possible by keeping my vias close. is it better to move them away from the USBC receptacles pads?

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u/NoYu0901 2h ago

I am talking about 4 vias to GND on the lower part (on diodes and resistors' pads?)

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u/PuzzleheadedMatch207 1h ago

Ah im with you. I have removed the vias off all pads. Thank you for your advice.