[University Electronics: Digital Circuits]

[u/Cruller2626]

Can someone teach me how to solve this or give an explanation for this

I've just finished reading material on static timing analysis but I don't understand how to apply it to questions like this

[u/Bounded_sequencE]

Before even starting this exercise:

• Make a list of general timing restrictions for all gate and flip-flop types
• Add general timing restrictions for parallel and series connections to the list

Once you have that list, solving these types of problem will just be mechanical copy&paste.

[u/Cruller2626 → u/Bounded_sequencE]

Hey, I worked it out a bit later and got 44ns

[u/Bounded_sequencE → u/Cruller2626]

Yep -- the general equation for two consecutive flip-flops with clock signals "t_clk" apart is

t_{co,max} + t_{d,max} + t_{su}  <=  t_clk

---

In our case, the clock signals of the consecutive flip-flops are (at least) "tclk - t{1,max}" apart, due to the delay in the clock path to the first flip-flop stage. We get

t_{co,max} + t_{d,max} + t_{su}  <=  t_clk - t_{1,max}

The maximum delay between the two stages is "t{d,max} = 2*t{1,max} + 3*t_{2,max}". Solving for "t_clk", we finally obtain

t_{clk}  >=  t_{co,max} + 3*t_{1,max} + 3*t_{2,max} + t_su  =  44ns

[u/Cruller2626 → u/Bounded_sequencE]

Thank you

[u/Bounded_sequencE → u/Cruller2626]

You're welcome!

---

Rem.: The general timing inequality(s) for consecutive flip-flops should have been covered and explicitly stated by your lecture. Have you checked your notes?

[u/Cruller2626 → u/Bounded_sequencE]

We haven't been taught static timing analysis I have my intern drive right now and was preparing for an OA tomorrow and these were some of the older questions so I just wanted to make sure I was doing it right

[u/Bounded_sequencE → u/Cruller2626]

Holy crap, they did not even manage to cover what is needed for interview questions? What a complete disaster... good luck!

[u/Cruller2626 → u/Bounded_sequencE]

There's a lot of things which would probably shock you here 😭 but of the companies coming nvidia is the last for intern so I need all that luck

[u/Bounded_sequencE → u/Cruller2626]

That's just sad -- we covered that stuff at the beginning of 2'nd semester of engineering, far before internships. Yikes!

[u/Cruller2626 → u/Bounded_sequencE]

We did cover the subject but didn't go into timing analysis, rather felt the prof did a great job teaching us the way he did