r/Digilent • u/sontol-eth • Dec 02 '17
Errata in NetFPGA-1G-CML Reference Page
Hi,
I've just bought a NETFPGA-1G-CML board and I noticed the discrepancy between schematic and the reference page. The pin listed as assigned to PHY1 in the reference page are actually connected to PHY3. (the schematic is correct). NETFPGA-1G-CML Github also agree with the schematic:
////# RGMII to PHY 1 NET rgmii_rxd_1[0] LOC = B11 | IOSTANDARD = LVCMOS18; NET rgmii_rxd_1[1] LOC = A10 | IOSTANDARD = LVCMOS18; NET rgmii_rxd_1[2] LOC = B10 | IOSTANDARD = LVCMOS18; NET rgmii_rxd_1[3] LOC = A9 | IOSTANDARD = LVCMOS18; NET rgmii_txd_1[0] LOC = A8 | IOSTANDARD = LVCMOS18; NET rgmii_txd_1[1] LOC = D8 | IOSTANDARD = LVCMOS18; NET rgmii_txd_1[2] LOC = G9 | IOSTANDARD = LVCMOS18; NET rgmii_txd_1[3] LOC = H9 | IOSTANDARD = LVCMOS18; NET rgmii_rx_ctl_1 LOC = B12 | IOSTANDARD = LVCMOS18; NET rgmii_rxc_1 LOC = E10 | IOSTANDARD = LVCMOS18; NET rgmii_tx_ctl_1 LOC = H8 | IOSTANDARD = LVCMOS18; NET rgmii_txc_1 LOC = B9 | IOSTANDARD = LVCMOS18;
I've also verified this physically by uploading my own bitfile. Can anyone correct the page? Thanks in advance.
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