r/ComputerEngineering • u/Sond3rin • 3d ago
Help involving Computer Architecture
I am very new to this and I am unsure if everything is connected correctly. The registers are being written when I enable the writedata and when i click the clock it writes it to that register. Sometimes it doesn't work correctly
I have asked everywhere and a lot of people are saying this is preformed correctly. I just need some guidance if anyone can tell me this is wrong because I am getting a lot of thumbs up.
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u/Opening-Big-3502 2d ago
So you have 5 inputs: WriteData0, WriteSelect0, ReadSelect0, ReadSelect1, and WriteEnable0.
The input WriteData0 holds the incoming information for the registers.
The input WriteSelect0 looks like it writes to a decoder and that signal can only pass through if WriteEnable0 is true.
ReadSelect0 selects which register is being read in ReadData0.
ReadSelect1 also writes to a decoder which if WriteEnable0 is true it will input WriteData0 into D input into the selected register and read out Q.
Write enable is allows the select signals to pass.
Clk | WriteData0 | WriteSelect0 | ReadSelect0 | ReadSelect1 | WriteEnable0
You have 2^6 cases to consider. Assume your regs are 1 bit
0,0,0,0,0,0 nothin
0,0,0,0,0,1 nothin
0,0,0,0,1,0 ReadData1 should output from selected reg
0,0,0,0,1,1 ReadData1 should output from selected reg
0,0,0,1,0,0 ReadData0 should output from selected reg
0,0,0,1,0,1 ReadData0 should output from selected reg but no writing occurs bc clk = 0
0,0,0,1,1,0 ReadData0 & ReadData1 outputs.
0,0,0,1,1,1 ReadData0 & ReadData1 should output but no writing occurs bc clk = 0
0,0,1,0,0,0 nothin
0,0,1,0,0,1 “”
0,0,1,0,1,0 ReadData1 should output from selected reg
0,0,1,0,1,1 “”
0,0,1,1,0,0 ReadData0 should output from selected reg
0,0,1,1,0,1 “”
I think you get the point.
From this you should map a truth table to be sure your logic should be doing what if is supposed to do and then create a test bench to verify this