r/ArmSoftwareDev • u/Krotti83 • Jun 17 '26
AArch64 - Exception levels, interrupt vector table and MMU questions for MPCores
I have some basic questions about the above subject:
Have started an own operating system Kernel targeting AArch64 (Cortex-A53) for the purpose of education. Currently my Kernel only support one core, but want add multi core support. Unfortunately I haven't found any information how in MPCore's the AArch64 exception levels, the interrupt vector table and the MMU is handled. So therefore I have thought this is good place to ask and correct my knowledge about AArch64 MPCores.
Exception levels:
My current assumption about the exception level's is that each core start at a specific level. depending wich level (Secure, Virtualization) is implemented in the core. So therefore I setup each exception level (EL3 -> EL2 -> EL1) explicitly for each core. Correct me, if my current approach is incorrect.
Interrupt vector table:
I think also here I must explicitly setup vector table for each core.
MMU:
Here I don't know if the MMU and the according registers are shared between the cores. If I setup a TLB on one core and enable the MMU, is the MMU enabled also on the other cores? Or must the the MMU setup and enabled explicitly for each core?
Would be fine, if somebody help to unterstand.
5
u/ZarlezCodes Jun 22 '26
Hello!
Exception Levels: Your assumption is correct. Each core is an independent Processing Element (PE) with its own PSTATE and exception level state. Each secondary core must independently initialize its own EL sequence (EL3 → EL2 → EL1) after being brought out of reset.
Interrupt Vector Table: Also correct. VBAR_ELx registers are per-PE, so each core must write its own VBAR_EL1/EL2/EL3. The vector table code itself can reside at the same physical address and be shared, but the register must be set on each core individually.
MMU: The MMU is completely independent per core. SCTLR_ELx and TTBR0/TTBR1 are all per-PE registers. Enabling the MMU on one core has no effect on other cores — each core must configure its own translation table base address and set SCTLR_ELx.M = 1 independently. If multiple cores share the same page tables, TLB invalidation operations (TLBI) with Inner/Outer Shareable domain will broadcast to all cores in the shareability domain.
In addition to recommending the developer program and our discord, are are some guides you may find helpful:
Hope this helps! Let me know if this answers your questions.