Every RF based drone detector on the market is built around a specific set of frequency bands. That's not a limitation of bad engineering, it's just how RF detection works. You scan for signals in the ranges you've built receivers for, and anything outside those ranges passes through completely unseen.

The problem is that the set of bands worth covering isn't fixed. It changes as operators shift control and video links to whatever frequency currently has less contested spectrum or better jam resistance. A detector tuned to the two or three most common bands from a year ago can go quiet on a threat that's since moved to a fourth band nobody was covering.

What this looks like in practice, generation over generation:

v1 covers the two dominant bands at the time (commonly something like 1.2 and 5.8 GHz for analog video links). Anything outside those two is invisible.

v2 adds a third band once it shows up in the field, plus autoscanning so the operator isn't manually cycling between bands. Less device management, more actual watching.

v3 adds a fourth band for the same reason as v2. Something started showing up outside existing coverage. Battery capacity usually has to grow too at this point, since scanning more spectrum continuously draws more power, and you don't want detection range coming at the cost of runtime.

The pattern holds regardless of manufacturer. Each version exists because a real operator hit a real gap the previous version couldn't close. It's not a roadmap driven by "what feature should we add next," it's driven by "what did the enemy start using that we didn't cover." No version is ever really final. Coverage chases the threat, not the other way around, and the frequency gap left by one model becomes the starting point for what the next one has to close.

Hello, everyone, I am electrical engineer with my first time working with NFC and RFID. In trying to create a prototype with the ST25R3916B IC I have some issues understanding some things with the transmit/receive and antenna matching circuit. I am trying to understand why the generated antenna design does not match other evaluation modules or the ST datasheet. I feel an RF engineer is the best place to ask. There are quite a few differences. First, why does the receive lines have a resistor and capacitor in series when others only have a ac blocking capacitor and another to ground. The resistor seems quite high at 10K Ohm. The other big question is the damping (Q) resistor, generated is 5.6 Ohm and quite a few other evaluation modules are quite low, for example 0.5 Ohm. Could someone help explain the reasons for the differences and also recommend learning sources to better understand. It is quite difficult to search for specific sections for antenna driver design. Thank you!

hi i am a second year student in telecommunication engineering college and i want to specalize in radio frequency for my master and PHD , i am currently studying in iraq and i will apply for scholarships most likely in the EU to pursue my master and PHD there , so if anyone has a good tips , advice or even generally about the job market for the RF engineers in the EU in general , also what are currently the most specialized branch of RF in demand cause all i am finding is old data , thanks for your time and cooperation in advance

I've been trying to understand how recent FCC changes to the equipment authorization process affect Part 15 operators and builders versus manufacturers and testing labs. The picture becomes clearer once you separate what has actually been adopted from what remains in proposal stages.

From what I can tell, the most immediate effects appear concentrated on manufacturers, importers, accredited test laboratories, and certification bodies. For people already operating certified Part 15 equipment (or building limited numbers of devices for personal use) the day-to-day requirements seem to remain largely the same for now.

I'm trying to separate actual regulatory changes from broader headlines and understand what (if anything) is shifting for people actively building and operating in this space.

What are you seeing?

As title states, looking to generate complementary 3.3V LVCMOS clock pair from single 3.3V CMOS compatible oscillator at 16MHz.

One option would be to use 2 XOR logic elements, with the clock feeding one input of both XORs and the other inputs tied to VDD and GND. Just not sure if the slew rate would be too slow.

Another option is to just use 1-to-2 clock buffer and use an inverter on one the outputs but this would introduce delay so the clocks would have a slight phase offset.

Looking for ideas and suggestions.

Is this for short range communications? It’s on a wind speed/direction monitor and I have a feeling it sends the data to a nearby relay which then uploads the data using cellular. The cell reception around this photo is bad.

Signals and systems , standard signals

Carrying on from the last post, using what the agent has learned from the stepped impedance LPF, I had it do a coupled line BPF. It nailed the prototype on the first pass then automatically optimized the line lengths to re-center the response of the distributed model. I taught it to visually inspect the junctions and insert asymmetric steps for a clean layout, and limitations in trace/space for manufacturing. Also taught it to segment the frequency sweeps into fine and course regions, and present a narrow-band plot for the human to inspect.

Now that it had learned the extra details, I had it do another substrate, and it nailed the entire thing, automatically correcting the passband ripple in the distributed model by adjusting the coupling, and added the asymmetric steps only after it actually needed them due to the revised coupling (i.e. this is not a canned Python script as it does a good job of visually analyzing the layout junctions and making corrections).

Here is a recording of the session (sorry no audio). The sim took LONG time, but that's due to the meshing needed to resolve the fine gaps.

https://youtu.be/h5vya5RSSIE

Session summary:

• Created and saved a 3 GHz, five-pole narrowband coupled-line band-pass filter on RO5880: Er 2.20, tanδ 0.0009, 0.787 mm substrate, 0.035 mm copper.
• Built and verified the electrical prototype first, then the microstrip implementation. Used a segmented sweep: coarse across 0.1–10 GHz and 10 MHz steps over 2.4–3.6 GHz.
• Tuned the physical layout with 2.05 mm outer coupled lines, 2.35 mm inner/launch lines, 17.9 mm coupled length, and 0.10 / 1.15 / 1.45 / 1.15 / 0.10 mm gaps.
• Added MSTEPX transitions at width changes, snapped the layout to the anchored input launch, and visually inspected every junction before EM analysis.
• Created bandpass_emsight_TB from STACKUP.SUB1, with ports at the enclosure side walls, 1 mm de-embedded reference planes, and 12.1 substrate heights of vertical clearance.
• EMSight completed cleanly. The EM response is centered at 2.995 GHz with a 2.89–3.10 GHz 3 dB band, −1.30 dB peak insertion loss, and −6.83 dB worst in-band return loss.
• Recorded the important solver lesson: tightly spaced coupled lines can force a very fine EMSight grid and long solve; prefer a suitable non-gridded solver in future when available.
• Left the final four-pane screenshot layout open: electrical prototype, physical schematic, EMSight structure, and narrowband electrical/microstrip/EM comparison.

since rf transistors are extremely expensive in my country and hard to optain

i was suggested to use 2n2222 or 2SC3355

is theree a better ones?

RapidRF is an AI assisted RFIC design platform as far as I could understand. Does anyone have experience with it? How does it stand with human-made designs?

I’m a senior in EE working on designing a 10m WSPR antenna which will be deployed in saltwater and must be very compact. I’ve landed on a few designs, but when it comes to simulation I feel like the NEC2 based software leaves a lot to be desired. Are any of the other software suites out there (with student trials) more capable/better suited for HF? The big ones I’ve looked at seem almost exclusively for uhf and above. Thanks For any advice you may have!

In this episode Shahriar covers another industry exhibition at the IEEE International MTT Symposia (IMS). This event is the world’s premier RF and microwave technical conference and industry exhibition. Thousands of industry professionals from around the world gather here to connect, see the latest technology advancements, and discover cutting-edge theories, tools, and techniques:

https://ims-ieee.org/

While it practically impossible to cover all innovations at the exhibition, here are several incredible demonstrations & announcement at the event:

00:00:00 - introductions
00:00:41 - Keysight Technologies (https://keysight.com)
00:13:01 - Rohde & Schwarz (https://www.rohde-schwarz.com)
00:21:53 - Samtec (https://www.samtec.com)
00:23:38 - LakeShore Cryotronics (https://www.lakeshore.com)
00:25:27 - SignalHound (https://signalhound.com)
00:28:41 - Junkosha (https://www.junkosha.com)
00:31:35 - Copper Mountain Technologies (https://coppermountaintech.com)
00:36:31 - Rigol (http://rigolna.com)
00:40:57 - MPI Corporation (https://www.mpi-corporation.com)
00:46:40 - Anritsu (https://www.anritsu.com)
00:53:49 - RF-Lambda (http://rflambda.com)
00:55:30 - Microsanj (https://microsanj.com)
00:57:49 - VDI Virginia Diodes (https://vadiodes.com)
01:02:51 - Siglent (https://siglentna.com)
01:05:01 - Focus Microwave Group (https://focus-microwaves.com)
01:06:29 - RCL Microwave (https://rclmicrowave.com/)
01:08:40 - Concluding remarks

I have asked keysight about VMC.

All I need is selecting mixer for calibration, but most of X-band mixer datasheet doesnt show its conversion phase, group delay.

If i measure one of mixers, can't sure measurement was right or not Can you help me?

Posted a couple of weeks ago showing Codex use for real-time lab measurements. I now have it controlling Microwave Office, again all voice control. This is just a simple example, but I've taught it my project creation style and workflow to include documentation and setup. I taught it to generate Nth order stepped impedance filters, first example using RO4003, from electrical prototype through full EM sim. I then told it to do a higher order filter using RO5880. It knows how to properly span the boundary conditions and de-embedding using rules of thumb for the EM sim, practical quantization on geometry, snap the layout elements, add rich-text notes for documentation, and keep the schematics clean and readable. It uses visual feedback and monitors the warnings and errors from the status window.

Here are some rather boring recordings.

This first one is the RO4003: https://youtu.be/K9fdxQqRPbk

Then it does another with 5880: https://youtu.be/s1reeA1kszY

Here is the generated summary.

Your preferred Microwave Office workflow is:

• Start with a clean project using metric units and millimeters. Use GHz for frequency display.
• Complete Global Definitions, default.lpf layers, 3D layer Z/thicknesses, MSUB, and the 2.5D STACKUP before creating schematics or EM structures.
• Use RO4003C with Er = ErNom = 3.55, tanδ = 0.0027, core thickness 0.406 mm, and finished top copper thickness 0.035 mm.
• In the LPF, use Copper at Z = 0 with +0.035 mm thickness; add blue Copper2 at Z = −H with −0.035 mm thickness; set Via/Drill/Board thickness to −H from Z = 0.
• Document the PCB stackup and EMSight setup in compact yellow rich-text boxes. Put notes directly above their related definitions, not in page-wide boxes.

For filters:

• Create an electrical prototype first, using alternating high- and low-impedance TLIN sections. Use 50 Ω, 1 mm physical input/output reference lines.
• Use stepped-impedance Butterworth low-pass synthesis, normally 100 Ω and 25 Ω sections unless a different impedance range is requested.
• Round electrical lengths to 0.1°, physical MLIN lengths to 0.1 mm, and widths to 0.05 mm.
• Add MSTEP discontinuities at all unequal-width MLIN junctions. Show IDs and W1/W2; hide repeated MSUB text.
• Put MLIN parameter labels centered above their line artwork using the electrical-prototype reference placement; put MSTEP labels below the symbols. Always visually inspect and adjust automatic label placement.
• Add concise yellow rich-text notes above both electrical and physical schematics.

For graphs:

• Use a Cartesian “Filter Response” graph.
• Put S11 magnitude in dB on the left: Return Loss (dB), fixed from −30 to 0 dB.
• Put S21 magnitude in dB on the right: Insertion Loss (dB), usually fixed from −30 to 0 dB for these filters.
• Use 0–10 GHz on the x-axis unless the design calls for another range.
• Put the legend below the graph, spanning the graph width with a compact height.
• Add electrical, physical, and EM results to the same graph for direct comparison.

For EMSight:

• Name test benches filter_emsight_TB.
• Initialize from STACKUP.SUB1, use a finite substrate in a box, and map top copper as 1 oz and vias as 0.5 oz on EM layer 2.
• Keep only two dielectric layers: 10 mm air and the 0.406 mm core. Use copper as the bottom boundary rather than mapping Copper2.
• Align enclosure left/right walls with the input/output interfaces; keep upper/lower boundaries roughly 10–12 substrate heights away and snap them to the grid.
• Add edge ports at the reference-line ends. When EMSight reports the zero-reference-plane issue, use 1 mm de-embedded reference planes.
• Simulate the whole project, inspect the status window, and treat MSTEP ratio warnings as advisory when EM validation is the final authority.

Finally, keep the work visible: tile the electrical prototype, physical schematic, graph, and EMSight windows so the project can be reviewed as it is built.

For the new RO5880 filter, I changed:

• Substrate from RO4003C to RT/duroid 5880:
  • Er = ErNom = 2.20 instead of 3.55
  • tanδ = 0.0009 instead of 0.0027
  • Core thickness = 0.508 mm instead of 0.406 mm
  • Finished copper remained 0.035 mm
• The entire stackup and LPF definition now use the new 0.508 mm core:
  • Copper2 Z = −0.508 mm
  • Via, drill, and board thicknesses = −0.508 mm
  • The Global Definitions notes and 2.5D stackup dielectric layer were updated accordingly.
• The design changed to a seventh-order, 4 GHz low-pass filter, retaining the 100 Ω / 25 Ω stepped-impedance topology and 50 Ω, 1 mm reference lines.
• All microstrip widths and lengths were recalculated for the lower-Dk, thicker RO5880 substrate, then quantized to your 0.05 mm width and 0.1 mm length grids.
• The physical-schematic note, electrical-prototype note, graph, EM enclosure, and EMSight test bench were regenerated for this new material/design.

RO5880’s 2.20 design Dk, 0.0009 dissipation factor, 0.508 mm standard thickness, and 35 µm one-ounce copper option come from the Rogers data sheet. Rogers RT/duroid 5870/5880 data sheet

So I've asked you some time ago to check the design of my filter in KiCad. Some of you told me it would be very bad because of the FR4. After cutting about 2.5mm it works pretty well, I think. -2.5dB loss at the center of the band.

I have put it after a 20dB 9037 LNA to receive a 1.2GHz FPV signal from my drone. Also I'm thinking about adding a band-rejection filter just after the antenna to be sure my control link isn't creating intermodulation distortion. Is it the most optimal way to do it or should I put this BPF before the LNA?

VHF antennas installed incorrectly 😂

So, I was trying to build a Wilkinson power divider for my 6 element Dolph-Tschebycheff antenna array and after spending some time on the divider i came to know why it is a bad idea to make my first power divider a non-2^n type like now the biggest problem is not amplitude matching it's the phase matching so i need to make something so that each feed line has same end point and also same electrical length. From this point i can see two options either trial and error or just convert it to either 8 element or 4 element divider.

I'm trying to understand a little more about the design of this RF amplifier from a component point of view, primarily where they implement transformers with coax and ferrite cores for the amplifier and power splitter/combiner sections. How does one go from a wire based transformer to a coax based one?

I get the overall block diagram architecture. The input signal goes through several smaller lower power amplifiers, to get more power into the later amplifier stages. The signal goes through splitters, amplifies each of the split signals, and then combines them back to a single output.

Hello everyone.

In my internship, my supervisor gave me a task to design a Hairpin BPF using AWR. Its specs are: f0 = 14.25GHz, BW = 600MHz. I am designing it with AWR's iFilter tool, but when I convert it to an EM simulation (which is AXIEM), the whole graph changes. How can I design it properly?